@opcode(<NUM_LIT>, <NUM_LIT>, <NUM_LIT>) <EOL><INDENT>def instruction_LSR_memory(self, opcode, ea, m):<DEDENT>
r = self.LSR(m)<EOL><INDENT>log.debug("<STR_LIT>" % (<EOL>self.program_counter,<EOL>m, r, ea,<EOL>self.cfg.mem_info.get_shortest(ea)<EOL>))<EOL><DEDENT>return ea, r & <NUM_LIT><EOL>
Logical shift right memory location