def write(self, addr, data):
length = len(data)<EOL>for rmap in self.rmaps:<EOL><INDENT>regset = rmap.findRegisters(addr, length)<EOL>for reg in regset:<EOL><INDENT>if addr < reg.addr:<EOL><INDENT>data = data[reg.addr - addr:]<EOL>addr = reg.addr<EOL>reg_offs = <NUM_LIT:0><EOL>raise genicam.GenericException(<EOL>"<STR_LIT>" % (addr, length), "<STR_LIT>", <NUM_LIT:0>)<EOL><DEDENT>elif addr >= reg.addr:<EOL><INDENT>reg_offs = addr - reg.addr<EOL><DEDENT>write_len = min(length, reg.length - reg_offs)<EOL>reg.write(reg_offs, data[:write_len])<EOL>if write_len < len(data):<EOL><INDENT>raise genicam.GenericException(<EOL>"<STR_LIT>" % (addr, length), "<STR_LIT>", <NUM_LIT:0>)<EOL><DEDENT><DEDENT><DEDENT>
is called on a write to a register
if the write is misaligned, this method handles the read modify write of
the underlying registers
:param addr: base address of access
:param length: length of acces