@opcode(<EOL><NUM_LIT>, <EOL>)<EOL><INDENT>def instruction_CWAI(self, opcode, m):<DEDENT>
This instruction ANDs an immediate byte with the condition code register
which may clear the interrupt mask bits I and F, stacks the entire
machine state on the hardware stack and then looks for an interrupt.
When a non-masked interrupt occurs, no further machine state information
need be saved before vectoring to the interrupt handling routine. This
instruction replaced the MC6800 CLI WAI sequence, but does not place the
buses in a high-impedance state. A FIRQ (fast interrupt request) may
enter its interrupt handler with its entire machine state saved. The RTI
(return from interrupt) instruction will automatically return the entire
machine state after testing the E (entire) bit of the recovered
condition code register.

The following immediate values will have the following results: FF =
enable neither EF = enable IRQ BF = enable FIRQ AF = enable both

source code forms: CWAI #$XX E F H I N Z V C

CC bits "HNZVC": ddddd