@click.command('<STR_LIT>')<EOL>@click.pass_context<EOL>@click.option('<STR_LIT>', '<STR_LIT>', type=unicode, metavar='<STR_LIT>',<EOL>help='<STR_LIT>')<EOL>@click.option('<STR_LIT>', type=unicode, metavar='<STR_LIT>',<EOL>help='<STR_LIT>')<EOL>@click.option('<STR_LIT>', type=unicode, metavar='<STR_LIT:size>',<EOL>help='<STR_LIT>')<EOL>@click.option('<STR_LIT>', type=unicode, metavar='<STR_LIT:type>',<EOL>help='<STR_LIT>')<EOL>@click.option('<STR_LIT>', type=unicode, metavar='<STR_LIT>',<EOL>help='<STR_LIT>')<EOL>@click.option('<STR_LIT>', '<STR_LIT>', type=unicode, metavar='<STR_LIT:path>',<EOL>help='<STR_LIT>')<EOL>@click.option('<STR_LIT>', '<STR_LIT>', is_flag=True,<EOL>help='<STR_LIT>')<EOL>@click.option('<STR_LIT>', is_flag=True,<EOL>help='<STR_LIT>')<EOL>@click.option('<STR_LIT>', is_flag=True,<EOL>help='<STR_LIT>')<EOL>def cli(ctx, board, fpga, pack, type, size, project_dir,<EOL>verbose, verbose_yosys, verbose_arachne):
<EOL>exit_code = SCons(project_dir).build({<EOL>'<STR_LIT>': board,<EOL>'<STR_LIT>': fpga,<EOL>'<STR_LIT:size>': size,<EOL>'<STR_LIT:type>': type,<EOL>'<STR_LIT>': pack,<EOL>'<STR_LIT>': {<EOL>'<STR_LIT:all>': verbose,<EOL>'<STR_LIT>': verbose_yosys,<EOL>'<STR_LIT>': verbose_arachne<EOL>}<EOL>})<EOL>ctx.exit(exit_code)<EOL>
Synthesize the bitstream.