@opcode(<EOL><NUM_LIT>, <EOL>)<EOL><INDENT>def instruction_SWI3(self, opcode, ea, m):<DEDENT>
raise NotImplementedError("<STR_LIT>" % opcode)<EOL>
All of the processor registers are pushed onto the hardware stack (with
the exception of the hardware stack pointer itself), and control is
transferred through the software interrupt 3 vector. This interrupt does
not mask (disable) the normal and fast interrupts.

source code forms: SWI3

CC bits "HNZVC": -----