@opcode(<EOL><NUM_LIT>, <EOL>)<EOL><INDENT>def instruction_SWI(self, opcode):<DEDENT>
raise NotImplementedError("<STR_LIT>" % opcode)<EOL>
All of the processor registers are pushed onto the hardware stack (with
the exception of the hardware stack pointer itself), and control is
transferred through the software interrupt vector. Both the normal and
fast interrupts are masked (disabled).

source code forms: SWI

CC bits "HNZVC": -----