@opcode(<NUM_LIT>) <EOL><INDENT>def instruction_TFR(self, opcode, m):<DEDENT>
high, low = divmod(m, <NUM_LIT:16>)<EOL>dst_reg = self._get_register_obj(low)<EOL>src_reg = self._get_register_obj(high)<EOL>src_value = convert_differend_width(src_reg, dst_reg)<EOL>dst_reg.set(src_value)<EOL>
source code forms: TFR R1, R2
CC bits "HNZVC": ccccc