@opcode(<EOL><NUM_LIT>, <EOL>)<EOL><INDENT>def instruction_SEX(self, opcode):<DEDENT>
b = self.accu_b.value<EOL>if b & <NUM_LIT> == <NUM_LIT:0>:<EOL><INDENT>self.accu_a.set(<NUM_LIT>)<EOL><DEDENT>d = self.accu_d.value<EOL><INDENT>log.debug("<STR_LIT>", b, b, (b & <NUM_LIT>), d)<EOL><DEDENT>self.clear_NZ()<EOL>self.update_NZ_16(d)<EOL>
This instruction transforms a twos complement 8-bit value in accumulator
B into a twos complement 16-bit value in the D accumulator.

source code forms: SEX

CC bits "HNZVC": -aa0-

    // 0x1d SEX inherent
    case 0x1d:
        WREG_A = (RREG_B & 0x80) ? 0xff : 0;
        CLR_NZ;
        SET_NZ16(REG_D);
        peek_byte(cpu, REG_PC);

#define SIGNED(b) ((Word)(b&0x80?b|0xff00:b))
case 0x1D: /* SEX */ tw=SIGNED(ibreg); SETNZ16(tw) SETDREG(tw) break;