int ioinst_handle_tsch(S390CPU *cpu, uint64_t reg1, uint32_t ipb)

{

    CPUS390XState *env = &cpu->env;

    int cssid, ssid, schid, m;

    SubchDev *sch;

    IRB irb;

    uint64_t addr;

    int cc, irb_len;

    uint8_t ar;



    if (ioinst_disassemble_sch_ident(reg1, &m, &cssid, &ssid, &schid)) {

        program_interrupt(env, PGM_OPERAND, 2);

        return -EIO;

    }

    trace_ioinst_sch_id("tsch", cssid, ssid, schid);

    addr = decode_basedisp_s(env, ipb, &ar);

    if (addr & 3) {

        program_interrupt(env, PGM_SPECIFICATION, 2);

        return -EIO;

    }



    sch = css_find_subch(m, cssid, ssid, schid);

    if (sch && css_subch_visible(sch)) {

        cc = css_do_tsch_get_irb(sch, &irb, &irb_len);

    } else {

        cc = 3;

    }

    /* 0 - status pending, 1 - not status pending, 3 - not operational */

    if (cc != 3) {

        if (s390_cpu_virt_mem_write(cpu, addr, ar, &irb, irb_len) != 0) {

            return -EFAULT;

        }

        css_do_tsch_update_subch(sch);

    } else {

        irb_len = sizeof(irb) - sizeof(irb.emw);

        /* Access exceptions have a higher priority than cc3 */

        if (s390_cpu_virt_mem_check_write(cpu, addr, ar, irb_len) != 0) {

            return -EFAULT;

        }

    }



    setcc(cpu, cc);

    return 0;

}

int ioinst_handle_tsch(S390CPU *cpu, uint64_t reg1, uint32_t ipb)

{

    CPUS390XState *env = &cpu->env;

    int cssid, ssid, schid, m;

    SubchDev *sch;

    IRB irb;

    uint64_t addr;

    int cc, irb_len;

    uint8_t ar;



    if (ioinst_disassemble_sch_ident(reg1, &m, &cssid, &ssid, &schid)) {

        program_interrupt(env, PGM_OPERAND, 2);

        return -EIO;

    }

    trace_ioinst_sch_id("tsch", cssid, ssid, schid);

    addr = decode_basedisp_s(env, ipb, &ar);

    if (addr & 3) {

        program_interrupt(env, PGM_SPECIFICATION, 2);

        return -EIO;

    }



    sch = css_find_subch(m, cssid, ssid, schid);

    if (sch && css_subch_visible(sch)) {

        cc = css_do_tsch_get_irb(sch, &irb, &irb_len);

    } else {

        cc = 3;

    }

    

    if (cc != 3) {

        if (s390_cpu_virt_mem_write(cpu, addr, ar, &irb, irb_len) != 0) {

            return -EFAULT;

        }

        css_do_tsch_update_subch(sch);

    } else {

        irb_len = sizeof(irb) - sizeof(irb.emw);

        

        if (s390_cpu_virt_mem_check_write(cpu, addr, ar, irb_len) != 0) {

            return -EFAULT;

        }

    }



    setcc(cpu, cc);

    return 0;

}

int FUNC_0(S390CPU *VAR_0, uint64_t VAR_1, uint32_t VAR_2)

{

    CPUS390XState *env = &VAR_0->env;

    int VAR_3, VAR_4, VAR_5, VAR_6;

    SubchDev *sch;

    IRB irb;

    uint64_t addr;

    int VAR_7, VAR_8;

    uint8_t ar;



    if (ioinst_disassemble_sch_ident(VAR_1, &VAR_6, &VAR_3, &VAR_4, &VAR_5)) {

        program_interrupt(env, PGM_OPERAND, 2);

        return -EIO;

    }

    trace_ioinst_sch_id("tsch", VAR_3, VAR_4, VAR_5);

    addr = decode_basedisp_s(env, VAR_2, &ar);

    if (addr & 3) {

        program_interrupt(env, PGM_SPECIFICATION, 2);

        return -EIO;

    }



    sch = css_find_subch(VAR_6, VAR_3, VAR_4, VAR_5);

    if (sch && css_subch_visible(sch)) {

        VAR_7 = css_do_tsch_get_irb(sch, &irb, &VAR_8);

    } else {

        VAR_7 = 3;

    }

    

    if (VAR_7 != 3) {

        if (s390_cpu_virt_mem_write(VAR_0, addr, ar, &irb, VAR_8) != 0) {

            return -EFAULT;

        }

        css_do_tsch_update_subch(sch);

    } else {

        VAR_8 = sizeof(irb) - sizeof(irb.emw);

        

        if (s390_cpu_virt_mem_check_write(VAR_0, addr, ar, VAR_8) != 0) {

            return -EFAULT;

        }

    }



    setcc(VAR_0, VAR_7);

    return 0;

}

int FUNC_0(S390CPU *VAR_0, uint64_t VAR_1, uint32_t VAR_2)
{ CPUS390XState *env = &VAR_0->env; int VAR_3, VAR_4, VAR_5, VAR_6; SubchDev *sch; IRB irb; uint64_t addr; int VAR_7, VAR_8; uint8_t ar; if (ioinst_disassemble_sch_ident(VAR_1, &VAR_6, &VAR_3, &VAR_4, &VAR_5)) { program_interrupt(env, PGM_OPERAND, 2); return -EIO; } trace_ioinst_sch_id("tsch", VAR_3, VAR_4, VAR_5); addr = decode_basedisp_s(env, VAR_2, &ar); if (addr & 3) { program_interrupt(env, PGM_SPECIFICATION, 2); return -EIO; } sch = css_find_subch(VAR_6, VAR_3, VAR_4, VAR_5); if (sch && css_subch_visible(sch)) { VAR_7 = css_do_tsch_get_irb(sch, &irb, &VAR_8); } else { VAR_7 = 3; } if (VAR_7 != 3) { if (s390_cpu_virt_mem_write(VAR_0, addr, ar, &irb, VAR_8) != 0) { return -EFAULT; } css_do_tsch_update_subch(sch); } else { VAR_8 = sizeof(irb) - sizeof(irb.emw); if (s390_cpu_virt_mem_check_write(VAR_0, addr, ar, VAR_8) != 0) { return -EFAULT; } } setcc(VAR_0, VAR_7); return 0; }