ser_write(void *opaque, target_phys_addr_t addr,

          uint64_t val64, unsigned int size)

{

    struct etrax_serial *s = opaque;

    uint32_t value = val64;

    unsigned char ch = val64;

    D(CPUCRISState *env = s->env);



    D(qemu_log("%s " TARGET_FMT_plx "=%x\n",  __func__, addr, value));

    addr >>= 2;

    switch (addr)

    {

        case RW_DOUT:

            qemu_chr_fe_write(s->chr, &ch, 1);

            s->regs[R_INTR] |= 3;

            s->pending_tx = 1;

            s->regs[addr] = value;

            break;

        case RW_ACK_INTR:

            if (s->pending_tx) {

                value &= ~1;

                s->pending_tx = 0;

                D(qemu_log("fixedup value=%x r_intr=%x\n",

                           value, s->regs[R_INTR]));

            }

            s->regs[addr] = value;

            s->regs[R_INTR] &= ~value;

            D(printf("r_intr=%x\n", s->regs[R_INTR]));

            break;

        default:

            s->regs[addr] = value;

            break;

    }

    ser_update_irq(s);

}

ser_write(void *opaque, target_phys_addr_t addr,

          uint64_t val64, unsigned int size)

{

    struct etrax_serial *s = opaque;

    uint32_t value = val64;

    unsigned char ch = val64;

    D(CPUCRISState *env = s->env);



    D(qemu_log("%s " TARGET_FMT_plx "=%x\n",  __func__, addr, value));

    addr >>= 2;

    switch (addr)

    {

        case RW_DOUT:

            qemu_chr_fe_write(s->chr, &ch, 1);

            s->regs[R_INTR] |= 3;

            s->pending_tx = 1;

            s->regs[addr] = value;

            break;

        case RW_ACK_INTR:

            if (s->pending_tx) {

                value &= ~1;

                s->pending_tx = 0;

                D(qemu_log("fixedup value=%x r_intr=%x\n",

                           value, s->regs[R_INTR]));

            }

            s->regs[addr] = value;

            s->regs[R_INTR] &= ~value;

            D(printf("r_intr=%x\n", s->regs[R_INTR]));

            break;

        default:

            s->regs[addr] = value;

            break;

    }

    ser_update_irq(s);

}

FUNC_0(void *VAR_0, target_phys_addr_t VAR_1,

          uint64_t VAR_2, unsigned int VAR_3)

{

    struct etrax_serial *VAR_4 = VAR_0;

    uint32_t value = VAR_2;

    unsigned char VAR_5 = VAR_2;

    D(CPUCRISState *env = VAR_4->env);



    D(qemu_log("%VAR_4 " TARGET_FMT_plx "=%x\n",  __func__, VAR_1, value));

    VAR_1 >>= 2;

    switch (VAR_1)

    {

        case RW_DOUT:

            qemu_chr_fe_write(VAR_4->chr, &VAR_5, 1);

            VAR_4->regs[R_INTR] |= 3;

            VAR_4->pending_tx = 1;

            VAR_4->regs[VAR_1] = value;

            break;

        case RW_ACK_INTR:

            if (VAR_4->pending_tx) {

                value &= ~1;

                VAR_4->pending_tx = 0;

                D(qemu_log("fixedup value=%x r_intr=%x\n",

                           value, VAR_4->regs[R_INTR]));

            }

            VAR_4->regs[VAR_1] = value;

            VAR_4->regs[R_INTR] &= ~value;

            D(printf("r_intr=%x\n", VAR_4->regs[R_INTR]));

            break;

        default:

            VAR_4->regs[VAR_1] = value;

            break;

    }

    ser_update_irq(VAR_4);

}

FUNC_0(void *VAR_0, target_phys_addr_t VAR_1,
uint64_t VAR_2, unsigned int VAR_3)
{ struct etrax_serial *VAR_4 = VAR_0; uint32_t value = VAR_2; unsigned char VAR_5 = VAR_2; D(CPUCRISState *env = VAR_4->env); D(qemu_log("%VAR_4 " TARGET_FMT_plx "=%x\n",  __func__, VAR_1, value)); VAR_1 >>= 2; switch (VAR_1)
{ case RW_DOUT:
qemu_chr_fe_write(VAR_4->chr, &VAR_5, 1); VAR_4->regs[R_INTR] |= 3; VAR_4->pending_tx = 1; VAR_4->regs[VAR_1] = value; break; case RW_ACK_INTR:
if (VAR_4->pending_tx) { value &= ~1; VAR_4->pending_tx = 0; D(qemu_log("fixedup value=%x r_intr=%x\n",
value, VAR_4->regs[R_INTR])); } VAR_4->regs[VAR_1] = value; VAR_4->regs[R_INTR] &= ~value; D(printf("r_intr=%x\n", VAR_4->regs[R_INTR])); break; default:
VAR_4->regs[VAR_1] = value; break; } ser_update_irq(VAR_4); }