int kvm_arch_put_registers(CPUState *env)

{

    struct kvm_regs regs;

    int ret;

    int i;



    ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, &regs);

    if (ret < 0)

        return ret;



    regs.ctr = env->ctr;

    regs.lr  = env->lr;

    regs.xer = env->xer;

    regs.msr = env->msr;

    regs.pc = env->nip;



    regs.srr0 = env->spr[SPR_SRR0];

    regs.srr1 = env->spr[SPR_SRR1];



    regs.sprg0 = env->spr[SPR_SPRG0];

    regs.sprg1 = env->spr[SPR_SPRG1];

    regs.sprg2 = env->spr[SPR_SPRG2];

    regs.sprg3 = env->spr[SPR_SPRG3];

    regs.sprg4 = env->spr[SPR_SPRG4];

    regs.sprg5 = env->spr[SPR_SPRG5];

    regs.sprg6 = env->spr[SPR_SPRG6];

    regs.sprg7 = env->spr[SPR_SPRG7];



    for (i = 0;i < 32; i++)

        regs.gpr[i] = env->gpr[i];



    ret = kvm_vcpu_ioctl(env, KVM_SET_REGS, &regs);

    if (ret < 0)

        return ret;



    return ret;

}

int kvm_arch_put_registers(CPUState *env)

{

    struct kvm_regs regs;

    int ret;

    int i;



    ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, &regs);

    if (ret < 0)

        return ret;



    regs.ctr = env->ctr;

    regs.lr  = env->lr;

    regs.xer = env->xer;

    regs.msr = env->msr;

    regs.pc = env->nip;



    regs.srr0 = env->spr[SPR_SRR0];

    regs.srr1 = env->spr[SPR_SRR1];



    regs.sprg0 = env->spr[SPR_SPRG0];

    regs.sprg1 = env->spr[SPR_SPRG1];

    regs.sprg2 = env->spr[SPR_SPRG2];

    regs.sprg3 = env->spr[SPR_SPRG3];

    regs.sprg4 = env->spr[SPR_SPRG4];

    regs.sprg5 = env->spr[SPR_SPRG5];

    regs.sprg6 = env->spr[SPR_SPRG6];

    regs.sprg7 = env->spr[SPR_SPRG7];



    for (i = 0;i < 32; i++)

        regs.gpr[i] = env->gpr[i];



    ret = kvm_vcpu_ioctl(env, KVM_SET_REGS, &regs);

    if (ret < 0)

        return ret;



    return ret;

}

int kvm_arch_put_registers(CPUState *env) int kvm_arch_put_registers(CPUState *env) int kvm_arch_put_registers(CPUState *env)
int FUNC_0(CPUState *VAR_0)

{

    struct kvm_regs VAR_1;

    int VAR_2;

    int VAR_3;



    VAR_2 = kvm_vcpu_ioctl(VAR_0, KVM_GET_REGS, &VAR_1);

    if (VAR_2 < 0)

        return VAR_2;



    VAR_1.ctr = VAR_0->ctr;

    VAR_1.lr  = VAR_0->lr;

    VAR_1.xer = VAR_0->xer;

    VAR_1.msr = VAR_0->msr;

    VAR_1.pc = VAR_0->nip;



    VAR_1.srr0 = VAR_0->spr[SPR_SRR0];

    VAR_1.srr1 = VAR_0->spr[SPR_SRR1];



    VAR_1.sprg0 = VAR_0->spr[SPR_SPRG0];

    VAR_1.sprg1 = VAR_0->spr[SPR_SPRG1];

    VAR_1.sprg2 = VAR_0->spr[SPR_SPRG2];

    VAR_1.sprg3 = VAR_0->spr[SPR_SPRG3];

    VAR_1.sprg4 = VAR_0->spr[SPR_SPRG4];

    VAR_1.sprg5 = VAR_0->spr[SPR_SPRG5];

    VAR_1.sprg6 = VAR_0->spr[SPR_SPRG6];

    VAR_1.sprg7 = VAR_0->spr[SPR_SPRG7];



    for (VAR_3 = 0;VAR_3 < 32; VAR_3++)

        VAR_1.gpr[VAR_3] = VAR_0->gpr[VAR_3];



    VAR_2 = kvm_vcpu_ioctl(VAR_0, KVM_SET_REGS, &VAR_1);

    if (VAR_2 < 0)

        return VAR_2;



    return VAR_2;

}

int FUNC_0(CPUState *VAR_0)
{ struct kvm_regs VAR_1; int VAR_2; int VAR_3; VAR_2 = kvm_vcpu_ioctl(VAR_0, KVM_GET_REGS, &VAR_1); if (VAR_2 < 0)
return VAR_2; VAR_1.ctr = VAR_0->ctr; VAR_1.lr  = VAR_0->lr; VAR_1.xer = VAR_0->xer; VAR_1.msr = VAR_0->msr; VAR_1.pc = VAR_0->nip; VAR_1.srr0 = VAR_0->spr[SPR_SRR0]; VAR_1.srr1 = VAR_0->spr[SPR_SRR1]; VAR_1.sprg0 = VAR_0->spr[SPR_SPRG0]; VAR_1.sprg1 = VAR_0->spr[SPR_SPRG1]; VAR_1.sprg2 = VAR_0->spr[SPR_SPRG2]; VAR_1.sprg3 = VAR_0->spr[SPR_SPRG3]; VAR_1.sprg4 = VAR_0->spr[SPR_SPRG4]; VAR_1.sprg5 = VAR_0->spr[SPR_SPRG5]; VAR_1.sprg6 = VAR_0->spr[SPR_SPRG6]; VAR_1.sprg7 = VAR_0->spr[SPR_SPRG7]; for (VAR_3 = 0;VAR_3 < 32; VAR_3++) VAR_1.gpr[VAR_3] = VAR_0->gpr[VAR_3]; VAR_2 = kvm_vcpu_ioctl(VAR_0, KVM_SET_REGS, &VAR_1); if (VAR_2 < 0)
return VAR_2; return VAR_2; }