static void axidma_write(void *opaque, hwaddr addr,

                         uint64_t value, unsigned size)

{

    XilinxAXIDMA *d = opaque;

    struct Stream *s;

    int sid;



    sid = streamid_from_addr(addr);

    s = &d->streams[sid];



    addr = addr % 0x30;

    addr >>= 2;

    switch (addr) {

        case R_DMACR:

            /* Tailptr mode is always on.  */

            value |= DMACR_TAILPTR_MODE;

            /* Remember our previous reset state.  */

            value |= (s->regs[addr] & DMACR_RESET);

            s->regs[addr] = value;



            if (value & DMACR_RESET) {

                stream_reset(s);

            }



            if ((value & 1) && !stream_resetting(s)) {

                /* Start processing.  */

                s->regs[R_DMASR] &= ~(DMASR_HALTED | DMASR_IDLE);

            }

            stream_reload_complete_cnt(s);

            break;



        case R_DMASR:

            /* Mask away write to clear irq lines.  */

            value &= ~(value & DMASR_IRQ_MASK);

            s->regs[addr] = value;

            break;



        case R_TAILDESC:

            s->regs[addr] = value;

            s->regs[R_DMASR] &= ~DMASR_IDLE; /* Not idle.  */

            if (!sid) {

                stream_process_mem2s(s, d->tx_dev);

            }

            break;

        default:

            D(qemu_log("%s: ch=%d addr=" TARGET_FMT_plx " v=%x\n",

                  __func__, sid, addr * 4, (unsigned)value));

            s->regs[addr] = value;

            break;

    }

    if (sid == 1 && d->notify) {

        d->notify(d->notify_opaque);

        d->notify = NULL;

    }

    stream_update_irq(s);

}

static void axidma_write(void *opaque, hwaddr addr,

                         uint64_t value, unsigned size)

{

    XilinxAXIDMA *d = opaque;

    struct Stream *s;

    int sid;



    sid = streamid_from_addr(addr);

    s = &d->streams[sid];



    addr = addr % 0x30;

    addr >>= 2;

    switch (addr) {

        case R_DMACR:

            

            value |= DMACR_TAILPTR_MODE;

            

            value |= (s->regs[addr] & DMACR_RESET);

            s->regs[addr] = value;



            if (value & DMACR_RESET) {

                stream_reset(s);

            }



            if ((value & 1) && !stream_resetting(s)) {

                

                s->regs[R_DMASR] &= ~(DMASR_HALTED | DMASR_IDLE);

            }

            stream_reload_complete_cnt(s);

            break;



        case R_DMASR:

            

            value &= ~(value & DMASR_IRQ_MASK);

            s->regs[addr] = value;

            break;



        case R_TAILDESC:

            s->regs[addr] = value;

            s->regs[R_DMASR] &= ~DMASR_IDLE; 

            if (!sid) {

                stream_process_mem2s(s, d->tx_dev);

            }

            break;

        default:

            D(qemu_log("%s: ch=%d addr=" TARGET_FMT_plx " v=%x\n",

                  __func__, sid, addr * 4, (unsigned)value));

            s->regs[addr] = value;

            break;

    }

    if (sid == 1 && d->notify) {

        d->notify(d->notify_opaque);

        d->notify = NULL;

    }

    stream_update_irq(s);

}

static void FUNC_0(void *VAR_0, hwaddr VAR_1,

                         uint64_t VAR_2, unsigned VAR_3)

{

    XilinxAXIDMA *d = VAR_0;

    struct Stream *VAR_4;

    int VAR_5;



    VAR_5 = streamid_from_addr(VAR_1);

    VAR_4 = &d->streams[VAR_5];



    VAR_1 = VAR_1 % 0x30;

    VAR_1 >>= 2;

    switch (VAR_1) {

        case R_DMACR:

            

            VAR_2 |= DMACR_TAILPTR_MODE;

            

            VAR_2 |= (VAR_4->regs[VAR_1] & DMACR_RESET);

            VAR_4->regs[VAR_1] = VAR_2;



            if (VAR_2 & DMACR_RESET) {

                stream_reset(VAR_4);

            }



            if ((VAR_2 & 1) && !stream_resetting(VAR_4)) {

                

                VAR_4->regs[R_DMASR] &= ~(DMASR_HALTED | DMASR_IDLE);

            }

            stream_reload_complete_cnt(VAR_4);

            break;



        case R_DMASR:

            

            VAR_2 &= ~(VAR_2 & DMASR_IRQ_MASK);

            VAR_4->regs[VAR_1] = VAR_2;

            break;



        case R_TAILDESC:

            VAR_4->regs[VAR_1] = VAR_2;

            VAR_4->regs[R_DMASR] &= ~DMASR_IDLE; 

            if (!VAR_5) {

                stream_process_mem2s(VAR_4, d->tx_dev);

            }

            break;

        default:

            D(qemu_log("%VAR_4: ch=%d VAR_1=" TARGET_FMT_plx " v=%x\n",

                  __func__, VAR_5, VAR_1 * 4, (unsigned)VAR_2));

            VAR_4->regs[VAR_1] = VAR_2;

            break;

    }

    if (VAR_5 == 1 && d->notify) {

        d->notify(d->notify_opaque);

        d->notify = NULL;

    }

    stream_update_irq(VAR_4);

}

static void FUNC_0(void *VAR_0, hwaddr VAR_1,
uint64_t VAR_2, unsigned VAR_3)
{ XilinxAXIDMA *d = VAR_0; struct Stream *VAR_4; int VAR_5; VAR_5 = streamid_from_addr(VAR_1); VAR_4 = &d->streams[VAR_5]; VAR_1 = VAR_1 % 0x30; VAR_1 >>= 2; switch (VAR_1) { case R_DMACR:
VAR_2 |= DMACR_TAILPTR_MODE; VAR_2 |= (VAR_4->regs[VAR_1] & DMACR_RESET); VAR_4->regs[VAR_1] = VAR_2; if (VAR_2 & DMACR_RESET) { stream_reset(VAR_4); } if ((VAR_2 & 1) && !stream_resetting(VAR_4)) { VAR_4->regs[R_DMASR] &= ~(DMASR_HALTED | DMASR_IDLE); } stream_reload_complete_cnt(VAR_4); break; case R_DMASR:
VAR_2 &= ~(VAR_2 & DMASR_IRQ_MASK); VAR_4->regs[VAR_1] = VAR_2; break; case R_TAILDESC:
VAR_4->regs[VAR_1] = VAR_2; VAR_4->regs[R_DMASR] &= ~DMASR_IDLE; if (!VAR_5) { stream_process_mem2s(VAR_4, d->tx_dev); } break; default:
D(qemu_log("%VAR_4: ch=%d VAR_1=" TARGET_FMT_plx " v=%x\n",
__func__, VAR_5, VAR_1 * 4, (unsigned)VAR_2)); VAR_4->regs[VAR_1] = VAR_2; break; } if (VAR_5 == 1 && d->notify) { d->notify(d->notify_opaque); d->notify = NULL; } stream_update_irq(VAR_4); }