static int get_physical_address_code(CPUState *env,

                                     target_phys_addr_t *physical, int *prot,

                                     target_ulong address, int mmu_idx)

{

    unsigned int i;

    uint64_t context;



    int is_user = (mmu_idx == MMU_USER_IDX ||

                   mmu_idx == MMU_USER_SECONDARY_IDX);



    if ((env->lsu & IMMU_E) == 0 || (env->pstate & PS_RED) != 0) {

        /* IMMU disabled */

        *physical = ultrasparc_truncate_physical(address);

        *prot = PAGE_EXEC;

        return 0;

    }



    if (env->tl == 0) {

        /* PRIMARY context */

        context = env->dmmu.mmu_primary_context & 0x1fff;

    } else {

        /* NUCLEUS context */

        context = 0;

    }



    for (i = 0; i < 64; i++) {

        // ctx match, vaddr match, valid?

        if (ultrasparc_tag_match(&env->itlb[i],

                                 address, context, physical)) {

            // access ok?

            if ((env->itlb[i].tte & 0x4) && is_user) {

                if (env->immu.sfsr) /* Fault status register */

                    env->immu.sfsr = 2; /* overflow (not read before

                                             another fault) */

                env->immu.sfsr |= (is_user << 3) | 1;

                env->exception_index = TT_TFAULT;

#ifdef DEBUG_MMU

                printf("TFAULT at 0x%" PRIx64 "\n", address);

#endif

                return 1;

            }

            *prot = PAGE_EXEC;

            TTE_SET_USED(env->itlb[i].tte);

            return 0;

        }

    }

#ifdef DEBUG_MMU

    printf("TMISS at 0x%" PRIx64 "\n", address);

#endif

    /* Context is stored in DMMU (dmmuregs[1]) also for IMMU */

    env->immu.tag_access = (address & ~0x1fffULL) | context;

    env->exception_index = TT_TMISS;

    return 1;

}

static int get_physical_address_code(CPUState *env,

                                     target_phys_addr_t *physical, int *prot,

                                     target_ulong address, int mmu_idx)

{

    unsigned int i;

    uint64_t context;



    int is_user = (mmu_idx == MMU_USER_IDX ||

                   mmu_idx == MMU_USER_SECONDARY_IDX);



    if ((env->lsu & IMMU_E) == 0 || (env->pstate & PS_RED) != 0) {

        

        *physical = ultrasparc_truncate_physical(address);

        *prot = PAGE_EXEC;

        return 0;

    }



    if (env->tl == 0) {

        

        context = env->dmmu.mmu_primary_context & 0x1fff;

    } else {

        

        context = 0;

    }



    for (i = 0; i < 64; i++) {

        

        if (ultrasparc_tag_match(&env->itlb[i],

                                 address, context, physical)) {

            

            if ((env->itlb[i].tte & 0x4) && is_user) {

                if (env->immu.sfsr) 

                    env->immu.sfsr = 2; 



                env->immu.sfsr |= (is_user << 3) | 1;

                env->exception_index = TT_TFAULT;

#ifdef DEBUG_MMU

                printf("TFAULT at 0x%" PRIx64 "\n", address);

#endif

                return 1;

            }

            *prot = PAGE_EXEC;

            TTE_SET_USED(env->itlb[i].tte);

            return 0;

        }

    }

#ifdef DEBUG_MMU

    printf("TMISS at 0x%" PRIx64 "\n", address);

#endif

    

    env->immu.tag_access = (address & ~0x1fffULL) | context;

    env->exception_index = TT_TMISS;

    return 1;

}

static int FUNC_0(CPUState *VAR_0,

                                     target_phys_addr_t *VAR_1, int *VAR_2,

                                     target_ulong VAR_3, int VAR_4)

{

    unsigned int VAR_5;

    uint64_t context;



    int VAR_6 = (VAR_4 == MMU_USER_IDX ||

                   VAR_4 == MMU_USER_SECONDARY_IDX);



    if ((VAR_0->lsu & IMMU_E) == 0 || (VAR_0->pstate & PS_RED) != 0) {

        

        *VAR_1 = ultrasparc_truncate_physical(VAR_3);

        *VAR_2 = PAGE_EXEC;

        return 0;

    }



    if (VAR_0->tl == 0) {

        

        context = VAR_0->dmmu.mmu_primary_context & 0x1fff;

    } else {

        

        context = 0;

    }



    for (VAR_5 = 0; VAR_5 < 64; VAR_5++) {

        

        if (ultrasparc_tag_match(&VAR_0->itlb[VAR_5],

                                 VAR_3, context, VAR_1)) {

            

            if ((VAR_0->itlb[VAR_5].tte & 0x4) && VAR_6) {

                if (VAR_0->immu.sfsr) 

                    VAR_0->immu.sfsr = 2; 



                VAR_0->immu.sfsr |= (VAR_6 << 3) | 1;

                VAR_0->exception_index = TT_TFAULT;

#ifdef DEBUG_MMU

                printf("TFAULT at 0x%" PRIx64 "\n", VAR_3);

#endif

                return 1;

            }

            *VAR_2 = PAGE_EXEC;

            TTE_SET_USED(VAR_0->itlb[VAR_5].tte);

            return 0;

        }

    }

#ifdef DEBUG_MMU

    printf("TMISS at 0x%" PRIx64 "\n", VAR_3);

#endif

    

    VAR_0->immu.tag_access = (VAR_3 & ~0x1fffULL) | context;

    VAR_0->exception_index = TT_TMISS;

    return 1;

}

static int FUNC_0(CPUState *VAR_0,
target_phys_addr_t *VAR_1, int *VAR_2,
target_ulong VAR_3, int VAR_4)
{ unsigned int VAR_5; uint64_t context; int VAR_6 = (VAR_4 == MMU_USER_IDX ||
VAR_4 == MMU_USER_SECONDARY_IDX); if ((VAR_0->lsu & IMMU_E) == 0 || (VAR_0->pstate & PS_RED) != 0) { *VAR_1 = ultrasparc_truncate_physical(VAR_3); *VAR_2 = PAGE_EXEC; return 0; } if (VAR_0->tl == 0) { context = VAR_0->dmmu.mmu_primary_context & 0x1fff; } else { context = 0; } for (VAR_5 = 0; VAR_5 < 64; VAR_5++) { if (ultrasparc_tag_match(&VAR_0->itlb[VAR_5],
VAR_3, context, VAR_1)) { if ((VAR_0->itlb[VAR_5].tte & 0x4) && VAR_6) { if (VAR_0->immu.sfsr)
VAR_0->immu.sfsr = 2; VAR_0->immu.sfsr |= (VAR_6 << 3) | 1; VAR_0->exception_index = TT_TFAULT; #ifdef DEBUG_MMU
printf("TFAULT at 0x%" PRIx64 "\n", VAR_3); #endif
return 1; } *VAR_2 = PAGE_EXEC; TTE_SET_USED(VAR_0->itlb[VAR_5].tte); return 0; } } #ifdef DEBUG_MMU
printf("TMISS at 0x%" PRIx64 "\n", VAR_3); #endif
VAR_0->immu.tag_access = (VAR_3 & ~0x1fffULL) | context; VAR_0->exception_index = TT_TMISS; return 1; }