e1000e_set_icr(E1000ECore *core, int index, uint32_t val)

{

    if ((core->mac[ICR] & E1000_ICR_ASSERTED) &&

        (core->mac[CTRL_EXT] & E1000_CTRL_EXT_IAME)) {

        trace_e1000e_irq_icr_process_iame();

        e1000e_clear_ims_bits(core, core->mac[IAM]);

    }



    trace_e1000e_irq_icr_write(val, core->mac[ICR], core->mac[ICR] & ~val);

    core->mac[ICR] &= ~val;

    e1000e_update_interrupt_state(core);

}

e1000e_set_icr(E1000ECore *core, int index, uint32_t val)

{

    if ((core->mac[ICR] & E1000_ICR_ASSERTED) &&

        (core->mac[CTRL_EXT] & E1000_CTRL_EXT_IAME)) {

        trace_e1000e_irq_icr_process_iame();

        e1000e_clear_ims_bits(core, core->mac[IAM]);

    }



    trace_e1000e_irq_icr_write(val, core->mac[ICR], core->mac[ICR] & ~val);

    core->mac[ICR] &= ~val;

    e1000e_update_interrupt_state(core);

}

    trace_e1000e_irq_icr_write(val, core->mac[ICR], core->mac[ICR] & ~val);     core->mac[ICR] &= ~val;
FUNC_0(E1000ECore *VAR_0, int VAR_1, uint32_t VAR_2)

{

    if ((VAR_0->mac[ICR] & E1000_ICR_ASSERTED) &&

        (VAR_0->mac[CTRL_EXT] & E1000_CTRL_EXT_IAME)) {

        trace_e1000e_irq_icr_process_iame();

        e1000e_clear_ims_bits(VAR_0, VAR_0->mac[IAM]);

    }



    trace_e1000e_irq_icr_write(VAR_2, VAR_0->mac[ICR], VAR_0->mac[ICR] & ~VAR_2);

    VAR_0->mac[ICR] &= ~VAR_2;

    e1000e_update_interrupt_state(VAR_0);

}

FUNC_0(E1000ECore *VAR_0, int VAR_1, uint32_t VAR_2)
{ if ((VAR_0->mac[ICR] & E1000_ICR_ASSERTED) &&
(VAR_0->mac[CTRL_EXT] & E1000_CTRL_EXT_IAME)) { trace_e1000e_irq_icr_process_iame(); e1000e_clear_ims_bits(VAR_0, VAR_0->mac[IAM]); } trace_e1000e_irq_icr_write(VAR_2, VAR_0->mac[ICR], VAR_0->mac[ICR] & ~VAR_2); VAR_0->mac[ICR] &= ~VAR_2; e1000e_update_interrupt_state(VAR_0); }