static void dec_store(DisasContext *dc)

{

    TCGv t, *addr;

    unsigned int size;



    size = 1 << (dc->opcode & 3);



    if (size > 4 && (dc->tb_flags & MSR_EE_FLAG)

          && !(dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)) {

        tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);

        t_gen_raise_exception(dc, EXCP_HW_EXCP);

        return;

    }



    LOG_DIS("s%d%s\n", size, dc->type_b ? "i" : "");

    t_sync_flags(dc);

    /* If we get a fault on a dslot, the jmpstate better be in sync.  */

    sync_jmpstate(dc);

    addr = compute_ldst_addr(dc, &t);



    /* Verify alignment if needed.  */

    if ((dc->env->pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) {

        gen_helper_memalign(*addr, tcg_const_tl(dc->rd),

                            tcg_const_tl(1), tcg_const_tl(size - 1));

    }



    gen_store(dc, *addr, cpu_R[dc->rd], size);

    if (addr == &t)

        tcg_temp_free(t);

}

static void dec_store(DisasContext *dc)

{

    TCGv t, *addr;

    unsigned int size;



    size = 1 << (dc->opcode & 3);



    if (size > 4 && (dc->tb_flags & MSR_EE_FLAG)

          && !(dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)) {

        tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);

        t_gen_raise_exception(dc, EXCP_HW_EXCP);

        return;

    }



    LOG_DIS("s%d%s\n", size, dc->type_b ? "i" : "");

    t_sync_flags(dc);

    

    sync_jmpstate(dc);

    addr = compute_ldst_addr(dc, &t);



    

    if ((dc->env->pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) {

        gen_helper_memalign(*addr, tcg_const_tl(dc->rd),

                            tcg_const_tl(1), tcg_const_tl(size - 1));

    }



    gen_store(dc, *addr, cpu_R[dc->rd], size);

    if (addr == &t)

        tcg_temp_free(t);

}

static void FUNC_0(DisasContext *VAR_0)

{

    TCGv t, *addr;

    unsigned int VAR_1;



    VAR_1 = 1 << (VAR_0->opcode & 3);



    if (VAR_1 > 4 && (VAR_0->tb_flags & MSR_EE_FLAG)

          && !(VAR_0->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)) {

        tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);

        t_gen_raise_exception(VAR_0, EXCP_HW_EXCP);

        return;

    }



    LOG_DIS("s%d%s\n", VAR_1, VAR_0->type_b ? "i" : "");

    t_sync_flags(VAR_0);

    

    sync_jmpstate(VAR_0);

    addr = compute_ldst_addr(VAR_0, &t);



    

    if ((VAR_0->env->pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && VAR_1 > 1) {

        gen_helper_memalign(*addr, tcg_const_tl(VAR_0->rd),

                            tcg_const_tl(1), tcg_const_tl(VAR_1 - 1));

    }



    gen_store(VAR_0, *addr, cpu_R[VAR_0->rd], VAR_1);

    if (addr == &t)

        tcg_temp_free(t);

}

static void FUNC_0(DisasContext *VAR_0)
{ TCGv t, *addr; unsigned int VAR_1; VAR_1 = 1 << (VAR_0->opcode & 3); if (VAR_1 > 4 && (VAR_0->tb_flags & MSR_EE_FLAG)
&& !(VAR_0->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)) { tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP); t_gen_raise_exception(VAR_0, EXCP_HW_EXCP); return; } LOG_DIS("s%d%s\n", VAR_1, VAR_0->type_b ? "i" : ""); t_sync_flags(VAR_0); sync_jmpstate(VAR_0); addr = compute_ldst_addr(VAR_0, &t); if ((VAR_0->env->pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && VAR_1 > 1) { gen_helper_memalign(*addr, tcg_const_tl(VAR_0->rd),
tcg_const_tl(1), tcg_const_tl(VAR_1 - 1)); } gen_store(VAR_0, *addr, cpu_R[VAR_0->rd], VAR_1); if (addr == &t)
tcg_temp_free(t); }