static void DMA_run (void)

{

    struct dma_cont *d;

    int icont, ichan;

    int rearm = 0;

    static int running = 0;



    if (running) {

        rearm = 1;

        goto out;

    } else {

        running = 1;

    }



    d = dma_controllers;



    for (icont = 0; icont < 2; icont++, d++) {

        for (ichan = 0; ichan < 4; ichan++) {

            int mask;



            mask = 1 << ichan;



            if ((0 == (d->mask & mask)) && (0 != (d->status & (mask << 4)))) {

                channel_run (icont, ichan);

                rearm = 1;

            }

        }

    }



    running = 0;

out:

    if (rearm)

        qemu_bh_schedule_idle(dma_bh);

}

static void DMA_run (void)

{

    struct dma_cont *d;

    int icont, ichan;

    int rearm = 0;

    static int running = 0;



    if (running) {

        rearm = 1;

        goto out;

    } else {

        running = 1;

    }



    d = dma_controllers;



    for (icont = 0; icont < 2; icont++, d++) {

        for (ichan = 0; ichan < 4; ichan++) {

            int mask;



            mask = 1 << ichan;



            if ((0 == (d->mask & mask)) && (0 != (d->status & (mask << 4)))) {

                channel_run (icont, ichan);

                rearm = 1;

            }

        }

    }



    running = 0;

out:

    if (rearm)

        qemu_bh_schedule_idle(dma_bh);

}

static void FUNC_0 (void)

{

    struct dma_cont *VAR_0;

    int VAR_1, VAR_2;

    int VAR_3 = 0;

    static int VAR_4 = 0;



    if (VAR_4) {

        VAR_3 = 1;

        goto out;

    } else {

        VAR_4 = 1;

    }



    VAR_0 = dma_controllers;



    for (VAR_1 = 0; VAR_1 < 2; VAR_1++, VAR_0++) {

        for (VAR_2 = 0; VAR_2 < 4; VAR_2++) {

            int VAR_5;



            VAR_5 = 1 << VAR_2;



            if ((0 == (VAR_0->VAR_5 & VAR_5)) && (0 != (VAR_0->status & (VAR_5 << 4)))) {

                channel_run (VAR_1, VAR_2);

                VAR_3 = 1;

            }

        }

    }



    VAR_4 = 0;

out:

    if (VAR_3)

        qemu_bh_schedule_idle(dma_bh);

}

static void FUNC_0 (void)
{ struct dma_cont *VAR_0; int VAR_1, VAR_2; int VAR_3 = 0; static int VAR_4 = 0; if (VAR_4) { VAR_3 = 1; goto out; } else { VAR_4 = 1; } VAR_0 = dma_controllers; for (VAR_1 = 0; VAR_1 < 2; VAR_1++, VAR_0++) { for (VAR_2 = 0; VAR_2 < 4; VAR_2++) { int VAR_5; VAR_5 = 1 << VAR_2; if ((0 == (VAR_0->VAR_5 & VAR_5)) && (0 != (VAR_0->status & (VAR_5 << 4)))) { channel_run (VAR_1, VAR_2); VAR_3 = 1; } } } VAR_4 = 0; out:
if (VAR_3)
qemu_bh_schedule_idle(dma_bh); }