static void msix_mmio_writel(void *opaque, target_phys_addr_t addr,

                             uint32_t val)

{

    PCIDevice *dev = opaque;

    unsigned int offset = addr & (MSIX_PAGE_SIZE - 1) & ~0x3;

    int vector = offset / MSIX_ENTRY_SIZE;

    pci_set_long(dev->msix_table_page + offset, val);

    if (!msix_is_masked(dev, vector) && msix_is_pending(dev, vector)) {

        msix_clr_pending(dev, vector);

        msix_notify(dev, vector);

    }

}

static void msix_mmio_writel(void *opaque, target_phys_addr_t addr,

                             uint32_t val)

{

    PCIDevice *dev = opaque;

    unsigned int offset = addr & (MSIX_PAGE_SIZE - 1) & ~0x3;

    int vector = offset / MSIX_ENTRY_SIZE;

    pci_set_long(dev->msix_table_page + offset, val);

    if (!msix_is_masked(dev, vector) && msix_is_pending(dev, vector)) {

        msix_clr_pending(dev, vector);

        msix_notify(dev, vector);

    }

}

static void FUNC_0(void *VAR_0, target_phys_addr_t VAR_1,

                             uint32_t VAR_2)

{

    PCIDevice *dev = VAR_0;

    unsigned int VAR_3 = VAR_1 & (MSIX_PAGE_SIZE - 1) & ~0x3;

    int VAR_4 = VAR_3 / MSIX_ENTRY_SIZE;

    pci_set_long(dev->msix_table_page + VAR_3, VAR_2);

    if (!msix_is_masked(dev, VAR_4) && msix_is_pending(dev, VAR_4)) {

        msix_clr_pending(dev, VAR_4);

        msix_notify(dev, VAR_4);

    }

}

static void FUNC_0(void *VAR_0, target_phys_addr_t VAR_1,
uint32_t VAR_2)
{ PCIDevice *dev = VAR_0; unsigned int VAR_3 = VAR_1 & (MSIX_PAGE_SIZE - 1) & ~0x3; int VAR_4 = VAR_3 / MSIX_ENTRY_SIZE; pci_set_long(dev->msix_table_page + VAR_3, VAR_2); if (!msix_is_masked(dev, VAR_4) && msix_is_pending(dev, VAR_4)) { msix_clr_pending(dev, VAR_4); msix_notify(dev, VAR_4); } }