static void channel_load_g(struct fs_dma_ctrl *ctrl, int c)

{

	target_phys_addr_t addr = channel_reg(ctrl, c, RW_GROUP);



	/* Load and decode. FIXME: handle endianness.  */

	cpu_physical_memory_read (addr, 

				  (void *) &ctrl->channels[c].current_g, 

				  sizeof ctrl->channels[c].current_g);

}

static void channel_load_g(struct fs_dma_ctrl *ctrl, int c)

{

	target_phys_addr_t addr = channel_reg(ctrl, c, RW_GROUP);



	

	cpu_physical_memory_read (addr, 

				  (void *) &ctrl->channels[c].current_g, 

				  sizeof ctrl->channels[c].current_g);

}

static void FUNC_0(struct fs_dma_ctrl *VAR_0, int VAR_1)

{

	target_phys_addr_t addr = channel_reg(VAR_0, VAR_1, RW_GROUP);



	

	cpu_physical_memory_read (addr, 

				  (void *) &VAR_0->channels[VAR_1].current_g, 

				  sizeof VAR_0->channels[VAR_1].current_g);

}

static void FUNC_0(struct fs_dma_ctrl *VAR_0, int VAR_1)
{ target_phys_addr_t addr = channel_reg(VAR_0, VAR_1, RW_GROUP); cpu_physical_memory_read (addr,
(void *) &VAR_0->channels[VAR_1].current_g,
sizeof VAR_0->channels[VAR_1].current_g); }