int kvm_arch_get_registers(CPUState *env)

{

    struct kvm_regs regs;

    struct kvm_sregs sregs;

    int i, ret;



    ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, &regs);

    if (ret < 0)

        return ret;



    ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs);

    if (ret < 0)

        return ret;



    env->ctr = regs.ctr;

    env->lr = regs.lr;

    env->xer = regs.xer;

    env->msr = regs.msr;

    env->nip = regs.pc;



    env->spr[SPR_SRR0] = regs.srr0;

    env->spr[SPR_SRR1] = regs.srr1;



    env->spr[SPR_SPRG0] = regs.sprg0;

    env->spr[SPR_SPRG1] = regs.sprg1;

    env->spr[SPR_SPRG2] = regs.sprg2;

    env->spr[SPR_SPRG3] = regs.sprg3;

    env->spr[SPR_SPRG4] = regs.sprg4;

    env->spr[SPR_SPRG5] = regs.sprg5;

    env->spr[SPR_SPRG6] = regs.sprg6;

    env->spr[SPR_SPRG7] = regs.sprg7;



    for (i = 0;i < 32; i++)

        env->gpr[i] = regs.gpr[i];



#ifdef KVM_CAP_PPC_SEGSTATE

    if (kvm_check_extension(env->kvm_state, KVM_CAP_PPC_SEGSTATE)) {

        env->sdr1 = sregs.u.s.sdr1;



        /* Sync SLB */

#ifdef TARGET_PPC64

        for (i = 0; i < 64; i++) {

            ppc_store_slb(env, sregs.u.s.ppc64.slb[i].slbe,

                               sregs.u.s.ppc64.slb[i].slbv);

        }

#endif



        /* Sync SRs */

        for (i = 0; i < 16; i++) {

            env->sr[i] = sregs.u.s.ppc32.sr[i];

        }



        /* Sync BATs */

        for (i = 0; i < 8; i++) {

            env->DBAT[0][i] = sregs.u.s.ppc32.dbat[i] & 0xffffffff;

            env->DBAT[1][i] = sregs.u.s.ppc32.dbat[i] >> 32;

            env->IBAT[0][i] = sregs.u.s.ppc32.ibat[i] & 0xffffffff;

            env->IBAT[1][i] = sregs.u.s.ppc32.ibat[i] >> 32;

        }

    }

#endif



    return 0;

}

int kvm_arch_get_registers(CPUState *env)

{

    struct kvm_regs regs;

    struct kvm_sregs sregs;

    int i, ret;



    ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, &regs);

    if (ret < 0)

        return ret;



    ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs);

    if (ret < 0)

        return ret;



    env->ctr = regs.ctr;

    env->lr = regs.lr;

    env->xer = regs.xer;

    env->msr = regs.msr;

    env->nip = regs.pc;



    env->spr[SPR_SRR0] = regs.srr0;

    env->spr[SPR_SRR1] = regs.srr1;



    env->spr[SPR_SPRG0] = regs.sprg0;

    env->spr[SPR_SPRG1] = regs.sprg1;

    env->spr[SPR_SPRG2] = regs.sprg2;

    env->spr[SPR_SPRG3] = regs.sprg3;

    env->spr[SPR_SPRG4] = regs.sprg4;

    env->spr[SPR_SPRG5] = regs.sprg5;

    env->spr[SPR_SPRG6] = regs.sprg6;

    env->spr[SPR_SPRG7] = regs.sprg7;



    for (i = 0;i < 32; i++)

        env->gpr[i] = regs.gpr[i];



#ifdef KVM_CAP_PPC_SEGSTATE

    if (kvm_check_extension(env->kvm_state, KVM_CAP_PPC_SEGSTATE)) {

        env->sdr1 = sregs.u.s.sdr1;



        

#ifdef TARGET_PPC64

        for (i = 0; i < 64; i++) {

            ppc_store_slb(env, sregs.u.s.ppc64.slb[i].slbe,

                               sregs.u.s.ppc64.slb[i].slbv);

        }

#endif



        

        for (i = 0; i < 16; i++) {

            env->sr[i] = sregs.u.s.ppc32.sr[i];

        }



        

        for (i = 0; i < 8; i++) {

            env->DBAT[0][i] = sregs.u.s.ppc32.dbat[i] & 0xffffffff;

            env->DBAT[1][i] = sregs.u.s.ppc32.dbat[i] >> 32;

            env->IBAT[0][i] = sregs.u.s.ppc32.ibat[i] & 0xffffffff;

            env->IBAT[1][i] = sregs.u.s.ppc32.ibat[i] >> 32;

        }

    }

#endif



    return 0;

}

int FUNC_0(CPUState *VAR_0)

{

    struct kvm_regs VAR_1;

    struct kvm_sregs VAR_2;

    int VAR_3, VAR_4;



    VAR_4 = kvm_vcpu_ioctl(VAR_0, KVM_GET_REGS, &VAR_1);

    if (VAR_4 < 0)

        return VAR_4;



    VAR_4 = kvm_vcpu_ioctl(VAR_0, KVM_GET_SREGS, &VAR_2);

    if (VAR_4 < 0)

        return VAR_4;



    VAR_0->ctr = VAR_1.ctr;

    VAR_0->lr = VAR_1.lr;

    VAR_0->xer = VAR_1.xer;

    VAR_0->msr = VAR_1.msr;

    VAR_0->nip = VAR_1.pc;



    VAR_0->spr[SPR_SRR0] = VAR_1.srr0;

    VAR_0->spr[SPR_SRR1] = VAR_1.srr1;



    VAR_0->spr[SPR_SPRG0] = VAR_1.sprg0;

    VAR_0->spr[SPR_SPRG1] = VAR_1.sprg1;

    VAR_0->spr[SPR_SPRG2] = VAR_1.sprg2;

    VAR_0->spr[SPR_SPRG3] = VAR_1.sprg3;

    VAR_0->spr[SPR_SPRG4] = VAR_1.sprg4;

    VAR_0->spr[SPR_SPRG5] = VAR_1.sprg5;

    VAR_0->spr[SPR_SPRG6] = VAR_1.sprg6;

    VAR_0->spr[SPR_SPRG7] = VAR_1.sprg7;



    for (VAR_3 = 0;VAR_3 < 32; VAR_3++)

        VAR_0->gpr[VAR_3] = VAR_1.gpr[VAR_3];



#ifdef KVM_CAP_PPC_SEGSTATE

    if (kvm_check_extension(VAR_0->kvm_state, KVM_CAP_PPC_SEGSTATE)) {

        VAR_0->sdr1 = VAR_2.u.s.sdr1;



        

#ifdef TARGET_PPC64

        for (VAR_3 = 0; VAR_3 < 64; VAR_3++) {

            ppc_store_slb(VAR_0, VAR_2.u.s.ppc64.slb[VAR_3].slbe,

                               VAR_2.u.s.ppc64.slb[VAR_3].slbv);

        }

#endif



        

        for (VAR_3 = 0; VAR_3 < 16; VAR_3++) {

            VAR_0->sr[VAR_3] = VAR_2.u.s.ppc32.sr[VAR_3];

        }



        

        for (VAR_3 = 0; VAR_3 < 8; VAR_3++) {

            VAR_0->DBAT[0][VAR_3] = VAR_2.u.s.ppc32.dbat[VAR_3] & 0xffffffff;

            VAR_0->DBAT[1][VAR_3] = VAR_2.u.s.ppc32.dbat[VAR_3] >> 32;

            VAR_0->IBAT[0][VAR_3] = VAR_2.u.s.ppc32.ibat[VAR_3] & 0xffffffff;

            VAR_0->IBAT[1][VAR_3] = VAR_2.u.s.ppc32.ibat[VAR_3] >> 32;

        }

    }

#endif



    return 0;

}

int FUNC_0(CPUState *VAR_0)
{ struct kvm_regs VAR_1; struct kvm_sregs VAR_2; int VAR_3, VAR_4; VAR_4 = kvm_vcpu_ioctl(VAR_0, KVM_GET_REGS, &VAR_1); if (VAR_4 < 0)
return VAR_4; VAR_4 = kvm_vcpu_ioctl(VAR_0, KVM_GET_SREGS, &VAR_2); if (VAR_4 < 0)
return VAR_4; VAR_0->ctr = VAR_1.ctr; VAR_0->lr = VAR_1.lr; VAR_0->xer = VAR_1.xer; VAR_0->msr = VAR_1.msr; VAR_0->nip = VAR_1.pc; VAR_0->spr[SPR_SRR0] = VAR_1.srr0; VAR_0->spr[SPR_SRR1] = VAR_1.srr1; VAR_0->spr[SPR_SPRG0] = VAR_1.sprg0; VAR_0->spr[SPR_SPRG1] = VAR_1.sprg1; VAR_0->spr[SPR_SPRG2] = VAR_1.sprg2; VAR_0->spr[SPR_SPRG3] = VAR_1.sprg3; VAR_0->spr[SPR_SPRG4] = VAR_1.sprg4; VAR_0->spr[SPR_SPRG5] = VAR_1.sprg5; VAR_0->spr[SPR_SPRG6] = VAR_1.sprg6; VAR_0->spr[SPR_SPRG7] = VAR_1.sprg7; for (VAR_3 = 0;VAR_3 < 32; VAR_3++) VAR_0->gpr[VAR_3] = VAR_1.gpr[VAR_3]; #ifdef KVM_CAP_PPC_SEGSTATE
if (kvm_check_extension(VAR_0->kvm_state, KVM_CAP_PPC_SEGSTATE)) { VAR_0->sdr1 = VAR_2.u.s.sdr1; #ifdef TARGET_PPC64
for (VAR_3 = 0; VAR_3 < 64; VAR_3++) { ppc_store_slb(VAR_0, VAR_2.u.s.ppc64.slb[VAR_3].slbe,
VAR_2.u.s.ppc64.slb[VAR_3].slbv); } #endif
for (VAR_3 = 0; VAR_3 < 16; VAR_3++) { VAR_0->sr[VAR_3] = VAR_2.u.s.ppc32.sr[VAR_3]; } for (VAR_3 = 0; VAR_3 < 8; VAR_3++) { VAR_0->DBAT[0][VAR_3] = VAR_2.u.s.ppc32.dbat[VAR_3] & 0xffffffff; VAR_0->DBAT[1][VAR_3] = VAR_2.u.s.ppc32.dbat[VAR_3] >> 32; VAR_0->IBAT[0][VAR_3] = VAR_2.u.s.ppc32.ibat[VAR_3] & 0xffffffff; VAR_0->IBAT[1][VAR_3] = VAR_2.u.s.ppc32.ibat[VAR_3] >> 32; } } #endif
return 0; }