void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l)

{

    int i, was_irq_disabled = pci_irq_disabled(d);

    uint32_t config_size = pci_config_size(d);



    for (i = 0; i < l && addr + i < config_size; val >>= 8, ++i) {

        uint8_t wmask = d->wmask[addr + i];

        uint8_t w1cmask = d->w1cmask[addr + i];

        assert(!(wmask & w1cmask));

        d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask);

        d->config[addr + i] &= ~(val & w1cmask); /* W1C: Write 1 to Clear */

    }

    if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) ||

        ranges_overlap(addr, l, PCI_ROM_ADDRESS, 4) ||

        ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) ||

        range_covers_byte(addr, l, PCI_COMMAND))

        pci_update_mappings(d);



    if (range_covers_byte(addr, l, PCI_COMMAND))

        pci_update_irq_disabled(d, was_irq_disabled);

}

void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l)

{

    int i, was_irq_disabled = pci_irq_disabled(d);

    uint32_t config_size = pci_config_size(d);



    for (i = 0; i < l && addr + i < config_size; val >>= 8, ++i) {

        uint8_t wmask = d->wmask[addr + i];

        uint8_t w1cmask = d->w1cmask[addr + i];

        assert(!(wmask & w1cmask));

        d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask);

        d->config[addr + i] &= ~(val & w1cmask); 

    }

    if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) ||

        ranges_overlap(addr, l, PCI_ROM_ADDRESS, 4) ||

        ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) ||

        range_covers_byte(addr, l, PCI_COMMAND))

        pci_update_mappings(d);



    if (range_covers_byte(addr, l, PCI_COMMAND))

        pci_update_irq_disabled(d, was_irq_disabled);

}

    uint32_t config_size = pci_config_size(d);     for (i = 0; i < l && addr + i < config_size; val >>= 8, ++i) {
void FUNC_0(PCIDevice *VAR_0, uint32_t VAR_1, uint32_t VAR_2, int VAR_3)

{

    int VAR_4, VAR_5 = pci_irq_disabled(VAR_0);

    uint32_t config_size = pci_config_size(VAR_0);



    for (VAR_4 = 0; VAR_4 < VAR_3 && VAR_1 + VAR_4 < config_size; VAR_2 >>= 8, ++VAR_4) {

        uint8_t wmask = VAR_0->wmask[VAR_1 + VAR_4];

        uint8_t w1cmask = VAR_0->w1cmask[VAR_1 + VAR_4];

        assert(!(wmask & w1cmask));

        VAR_0->config[VAR_1 + VAR_4] = (VAR_0->config[VAR_1 + VAR_4] & ~wmask) | (VAR_2 & wmask);

        VAR_0->config[VAR_1 + VAR_4] &= ~(VAR_2 & w1cmask); 

    }

    if (ranges_overlap(VAR_1, VAR_3, PCI_BASE_ADDRESS_0, 24) ||

        ranges_overlap(VAR_1, VAR_3, PCI_ROM_ADDRESS, 4) ||

        ranges_overlap(VAR_1, VAR_3, PCI_ROM_ADDRESS1, 4) ||

        range_covers_byte(VAR_1, VAR_3, PCI_COMMAND))

        pci_update_mappings(VAR_0);



    if (range_covers_byte(VAR_1, VAR_3, PCI_COMMAND))

        pci_update_irq_disabled(VAR_0, VAR_5);

}

void FUNC_0(PCIDevice *VAR_0, uint32_t VAR_1, uint32_t VAR_2, int VAR_3)
{ int VAR_4, VAR_5 = pci_irq_disabled(VAR_0); uint32_t config_size = pci_config_size(VAR_0); for (VAR_4 = 0; VAR_4 < VAR_3 && VAR_1 + VAR_4 < config_size; VAR_2 >>= 8, ++VAR_4) { uint8_t wmask = VAR_0->wmask[VAR_1 + VAR_4]; uint8_t w1cmask = VAR_0->w1cmask[VAR_1 + VAR_4]; assert(!(wmask & w1cmask)); VAR_0->config[VAR_1 + VAR_4] = (VAR_0->config[VAR_1 + VAR_4] & ~wmask) | (VAR_2 & wmask); VAR_0->config[VAR_1 + VAR_4] &= ~(VAR_2 & w1cmask); } if (ranges_overlap(VAR_1, VAR_3, PCI_BASE_ADDRESS_0, 24) ||
ranges_overlap(VAR_1, VAR_3, PCI_ROM_ADDRESS, 4) ||
ranges_overlap(VAR_1, VAR_3, PCI_ROM_ADDRESS1, 4) ||
range_covers_byte(VAR_1, VAR_3, PCI_COMMAND))
pci_update_mappings(VAR_0); if (range_covers_byte(VAR_1, VAR_3, PCI_COMMAND))
pci_update_irq_disabled(VAR_0, VAR_5); }