void cpu_dump_state(CPUState *env, FILE *f,

                    int (*cpu_fprintf)(FILE *f, const char *fmt, ...),

                    int flags)

{

    int eflags, i, nb;

    char cc_op_name[32];

    static const char *seg_name[6] = { "ES", "CS", "SS", "DS", "FS", "GS" };



    if (kvm_enabled())

        kvm_arch_get_registers(env);



    eflags = env->eflags;

#ifdef TARGET_X86_64

    if (env->hflags & HF_CS64_MASK) {

        cpu_fprintf(f,

                    "RAX=%016" PRIx64 " RBX=%016" PRIx64 " RCX=%016" PRIx64 " RDX=%016" PRIx64 "\n"

                    "RSI=%016" PRIx64 " RDI=%016" PRIx64 " RBP=%016" PRIx64 " RSP=%016" PRIx64 "\n"

                    "R8 =%016" PRIx64 " R9 =%016" PRIx64 " R10=%016" PRIx64 " R11=%016" PRIx64 "\n"

                    "R12=%016" PRIx64 " R13=%016" PRIx64 " R14=%016" PRIx64 " R15=%016" PRIx64 "\n"

                    "RIP=%016" PRIx64 " RFL=%08x [%c%c%c%c%c%c%c] CPL=%d II=%d A20=%d SMM=%d HLT=%d\n",

                    env->regs[R_EAX],

                    env->regs[R_EBX],

                    env->regs[R_ECX],

                    env->regs[R_EDX],

                    env->regs[R_ESI],

                    env->regs[R_EDI],

                    env->regs[R_EBP],

                    env->regs[R_ESP],

                    env->regs[8],

                    env->regs[9],

                    env->regs[10],

                    env->regs[11],

                    env->regs[12],

                    env->regs[13],

                    env->regs[14],

                    env->regs[15],

                    env->eip, eflags,

                    eflags & DF_MASK ? 'D' : '-',

                    eflags & CC_O ? 'O' : '-',

                    eflags & CC_S ? 'S' : '-',

                    eflags & CC_Z ? 'Z' : '-',

                    eflags & CC_A ? 'A' : '-',

                    eflags & CC_P ? 'P' : '-',

                    eflags & CC_C ? 'C' : '-',

                    env->hflags & HF_CPL_MASK,

                    (env->hflags >> HF_INHIBIT_IRQ_SHIFT) & 1,

                    (int)(env->a20_mask >> 20) & 1,

                    (env->hflags >> HF_SMM_SHIFT) & 1,

                    env->halted);

    } else

#endif

    {

        cpu_fprintf(f, "EAX=%08x EBX=%08x ECX=%08x EDX=%08x\n"

                    "ESI=%08x EDI=%08x EBP=%08x ESP=%08x\n"

                    "EIP=%08x EFL=%08x [%c%c%c%c%c%c%c] CPL=%d II=%d A20=%d SMM=%d HLT=%d\n",

                    (uint32_t)env->regs[R_EAX],

                    (uint32_t)env->regs[R_EBX],

                    (uint32_t)env->regs[R_ECX],

                    (uint32_t)env->regs[R_EDX],

                    (uint32_t)env->regs[R_ESI],

                    (uint32_t)env->regs[R_EDI],

                    (uint32_t)env->regs[R_EBP],

                    (uint32_t)env->regs[R_ESP],

                    (uint32_t)env->eip, eflags,

                    eflags & DF_MASK ? 'D' : '-',

                    eflags & CC_O ? 'O' : '-',

                    eflags & CC_S ? 'S' : '-',

                    eflags & CC_Z ? 'Z' : '-',

                    eflags & CC_A ? 'A' : '-',

                    eflags & CC_P ? 'P' : '-',

                    eflags & CC_C ? 'C' : '-',

                    env->hflags & HF_CPL_MASK,

                    (env->hflags >> HF_INHIBIT_IRQ_SHIFT) & 1,

                    (int)(env->a20_mask >> 20) & 1,

                    (env->hflags >> HF_SMM_SHIFT) & 1,

                    env->halted);

    }



    for(i = 0; i < 6; i++) {

        cpu_x86_dump_seg_cache(env, f, cpu_fprintf, seg_name[i],

                               &env->segs[i]);

    }

    cpu_x86_dump_seg_cache(env, f, cpu_fprintf, "LDT", &env->ldt);

    cpu_x86_dump_seg_cache(env, f, cpu_fprintf, "TR", &env->tr);



#ifdef TARGET_X86_64

    if (env->hflags & HF_LMA_MASK) {

        cpu_fprintf(f, "GDT=     %016" PRIx64 " %08x\n",

                    env->gdt.base, env->gdt.limit);

        cpu_fprintf(f, "IDT=     %016" PRIx64 " %08x\n",

                    env->idt.base, env->idt.limit);

        cpu_fprintf(f, "CR0=%08x CR2=%016" PRIx64 " CR3=%016" PRIx64 " CR4=%08x\n",

                    (uint32_t)env->cr[0],

                    env->cr[2],

                    env->cr[3],

                    (uint32_t)env->cr[4]);

        for(i = 0; i < 4; i++)

            cpu_fprintf(f, "DR%d=%016" PRIx64 " ", i, env->dr[i]);

        cpu_fprintf(f, "\nDR6=%016" PRIx64 " DR7=%016" PRIx64 "\n",

                    env->dr[6], env->dr[7]);

    } else

#endif

    {

        cpu_fprintf(f, "GDT=     %08x %08x\n",

                    (uint32_t)env->gdt.base, env->gdt.limit);

        cpu_fprintf(f, "IDT=     %08x %08x\n",

                    (uint32_t)env->idt.base, env->idt.limit);

        cpu_fprintf(f, "CR0=%08x CR2=%08x CR3=%08x CR4=%08x\n",

                    (uint32_t)env->cr[0],

                    (uint32_t)env->cr[2],

                    (uint32_t)env->cr[3],

                    (uint32_t)env->cr[4]);

        for(i = 0; i < 4; i++)

            cpu_fprintf(f, "DR%d=%08x ", i, env->dr[i]);

        cpu_fprintf(f, "\nDR6=%08x DR7=%08x\n", env->dr[6], env->dr[7]);

    }

    if (flags & X86_DUMP_CCOP) {

        if ((unsigned)env->cc_op < CC_OP_NB)

            snprintf(cc_op_name, sizeof(cc_op_name), "%s", cc_op_str[env->cc_op]);

        else

            snprintf(cc_op_name, sizeof(cc_op_name), "[%d]", env->cc_op);

#ifdef TARGET_X86_64

        if (env->hflags & HF_CS64_MASK) {

            cpu_fprintf(f, "CCS=%016" PRIx64 " CCD=%016" PRIx64 " CCO=%-8s\n",

                        env->cc_src, env->cc_dst,

                        cc_op_name);

        } else

#endif

        {

            cpu_fprintf(f, "CCS=%08x CCD=%08x CCO=%-8s\n",

                        (uint32_t)env->cc_src, (uint32_t)env->cc_dst,

                        cc_op_name);

        }

    }

    if (flags & X86_DUMP_FPU) {

        int fptag;

        fptag = 0;

        for(i = 0; i < 8; i++) {

            fptag |= ((!env->fptags[i]) << i);

        }

        cpu_fprintf(f, "FCW=%04x FSW=%04x [ST=%d] FTW=%02x MXCSR=%08x\n",

                    env->fpuc,

                    (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11,

                    env->fpstt,

                    fptag,

                    env->mxcsr);

        for(i=0;i<8;i++) {

#if defined(USE_X86LDOUBLE)

            union {

                long double d;

                struct {

                    uint64_t lower;

                    uint16_t upper;

                } l;

            } tmp;

            tmp.d = env->fpregs[i].d;

            cpu_fprintf(f, "FPR%d=%016" PRIx64 " %04x",

                        i, tmp.l.lower, tmp.l.upper);

#else

            cpu_fprintf(f, "FPR%d=%016" PRIx64,

                        i, env->fpregs[i].mmx.q);

#endif

            if ((i & 1) == 1)

                cpu_fprintf(f, "\n");

            else

                cpu_fprintf(f, " ");

        }

        if (env->hflags & HF_CS64_MASK)

            nb = 16;

        else

            nb = 8;

        for(i=0;i<nb;i++) {

            cpu_fprintf(f, "XMM%02d=%08x%08x%08x%08x",

                        i,

                        env->xmm_regs[i].XMM_L(3),

                        env->xmm_regs[i].XMM_L(2),

                        env->xmm_regs[i].XMM_L(1),

                        env->xmm_regs[i].XMM_L(0));

            if ((i & 1) == 1)

                cpu_fprintf(f, "\n");

            else

                cpu_fprintf(f, " ");

        }

    }

}

void cpu_dump_state(CPUState *env, FILE *f,

                    int (*cpu_fprintf)(FILE *f, const char *fmt, ...),

                    int flags)

{

    int eflags, i, nb;

    char cc_op_name[32];

    static const char *seg_name[6] = { "ES", "CS", "SS", "DS", "FS", "GS" };



    if (kvm_enabled())

        kvm_arch_get_registers(env);



    eflags = env->eflags;

#ifdef TARGET_X86_64

    if (env->hflags & HF_CS64_MASK) {

        cpu_fprintf(f,

                    "RAX=%016" PRIx64 " RBX=%016" PRIx64 " RCX=%016" PRIx64 " RDX=%016" PRIx64 "\n"

                    "RSI=%016" PRIx64 " RDI=%016" PRIx64 " RBP=%016" PRIx64 " RSP=%016" PRIx64 "\n"

                    "R8 =%016" PRIx64 " R9 =%016" PRIx64 " R10=%016" PRIx64 " R11=%016" PRIx64 "\n"

                    "R12=%016" PRIx64 " R13=%016" PRIx64 " R14=%016" PRIx64 " R15=%016" PRIx64 "\n"

                    "RIP=%016" PRIx64 " RFL=%08x [%c%c%c%c%c%c%c] CPL=%d II=%d A20=%d SMM=%d HLT=%d\n",

                    env->regs[R_EAX],

                    env->regs[R_EBX],

                    env->regs[R_ECX],

                    env->regs[R_EDX],

                    env->regs[R_ESI],

                    env->regs[R_EDI],

                    env->regs[R_EBP],

                    env->regs[R_ESP],

                    env->regs[8],

                    env->regs[9],

                    env->regs[10],

                    env->regs[11],

                    env->regs[12],

                    env->regs[13],

                    env->regs[14],

                    env->regs[15],

                    env->eip, eflags,

                    eflags & DF_MASK ? 'D' : '-',

                    eflags & CC_O ? 'O' : '-',

                    eflags & CC_S ? 'S' : '-',

                    eflags & CC_Z ? 'Z' : '-',

                    eflags & CC_A ? 'A' : '-',

                    eflags & CC_P ? 'P' : '-',

                    eflags & CC_C ? 'C' : '-',

                    env->hflags & HF_CPL_MASK,

                    (env->hflags >> HF_INHIBIT_IRQ_SHIFT) & 1,

                    (int)(env->a20_mask >> 20) & 1,

                    (env->hflags >> HF_SMM_SHIFT) & 1,

                    env->halted);

    } else

#endif

    {

        cpu_fprintf(f, "EAX=%08x EBX=%08x ECX=%08x EDX=%08x\n"

                    "ESI=%08x EDI=%08x EBP=%08x ESP=%08x\n"

                    "EIP=%08x EFL=%08x [%c%c%c%c%c%c%c] CPL=%d II=%d A20=%d SMM=%d HLT=%d\n",

                    (uint32_t)env->regs[R_EAX],

                    (uint32_t)env->regs[R_EBX],

                    (uint32_t)env->regs[R_ECX],

                    (uint32_t)env->regs[R_EDX],

                    (uint32_t)env->regs[R_ESI],

                    (uint32_t)env->regs[R_EDI],

                    (uint32_t)env->regs[R_EBP],

                    (uint32_t)env->regs[R_ESP],

                    (uint32_t)env->eip, eflags,

                    eflags & DF_MASK ? 'D' : '-',

                    eflags & CC_O ? 'O' : '-',

                    eflags & CC_S ? 'S' : '-',

                    eflags & CC_Z ? 'Z' : '-',

                    eflags & CC_A ? 'A' : '-',

                    eflags & CC_P ? 'P' : '-',

                    eflags & CC_C ? 'C' : '-',

                    env->hflags & HF_CPL_MASK,

                    (env->hflags >> HF_INHIBIT_IRQ_SHIFT) & 1,

                    (int)(env->a20_mask >> 20) & 1,

                    (env->hflags >> HF_SMM_SHIFT) & 1,

                    env->halted);

    }



    for(i = 0; i < 6; i++) {

        cpu_x86_dump_seg_cache(env, f, cpu_fprintf, seg_name[i],

                               &env->segs[i]);

    }

    cpu_x86_dump_seg_cache(env, f, cpu_fprintf, "LDT", &env->ldt);

    cpu_x86_dump_seg_cache(env, f, cpu_fprintf, "TR", &env->tr);



#ifdef TARGET_X86_64

    if (env->hflags & HF_LMA_MASK) {

        cpu_fprintf(f, "GDT=     %016" PRIx64 " %08x\n",

                    env->gdt.base, env->gdt.limit);

        cpu_fprintf(f, "IDT=     %016" PRIx64 " %08x\n",

                    env->idt.base, env->idt.limit);

        cpu_fprintf(f, "CR0=%08x CR2=%016" PRIx64 " CR3=%016" PRIx64 " CR4=%08x\n",

                    (uint32_t)env->cr[0],

                    env->cr[2],

                    env->cr[3],

                    (uint32_t)env->cr[4]);

        for(i = 0; i < 4; i++)

            cpu_fprintf(f, "DR%d=%016" PRIx64 " ", i, env->dr[i]);

        cpu_fprintf(f, "\nDR6=%016" PRIx64 " DR7=%016" PRIx64 "\n",

                    env->dr[6], env->dr[7]);

    } else

#endif

    {

        cpu_fprintf(f, "GDT=     %08x %08x\n",

                    (uint32_t)env->gdt.base, env->gdt.limit);

        cpu_fprintf(f, "IDT=     %08x %08x\n",

                    (uint32_t)env->idt.base, env->idt.limit);

        cpu_fprintf(f, "CR0=%08x CR2=%08x CR3=%08x CR4=%08x\n",

                    (uint32_t)env->cr[0],

                    (uint32_t)env->cr[2],

                    (uint32_t)env->cr[3],

                    (uint32_t)env->cr[4]);

        for(i = 0; i < 4; i++)

            cpu_fprintf(f, "DR%d=%08x ", i, env->dr[i]);

        cpu_fprintf(f, "\nDR6=%08x DR7=%08x\n", env->dr[6], env->dr[7]);

    }

    if (flags & X86_DUMP_CCOP) {

        if ((unsigned)env->cc_op < CC_OP_NB)

            snprintf(cc_op_name, sizeof(cc_op_name), "%s", cc_op_str[env->cc_op]);

        else

            snprintf(cc_op_name, sizeof(cc_op_name), "[%d]", env->cc_op);

#ifdef TARGET_X86_64

        if (env->hflags & HF_CS64_MASK) {

            cpu_fprintf(f, "CCS=%016" PRIx64 " CCD=%016" PRIx64 " CCO=%-8s\n",

                        env->cc_src, env->cc_dst,

                        cc_op_name);

        } else

#endif

        {

            cpu_fprintf(f, "CCS=%08x CCD=%08x CCO=%-8s\n",

                        (uint32_t)env->cc_src, (uint32_t)env->cc_dst,

                        cc_op_name);

        }

    }

    if (flags & X86_DUMP_FPU) {

        int fptag;

        fptag = 0;

        for(i = 0; i < 8; i++) {

            fptag |= ((!env->fptags[i]) << i);

        }

        cpu_fprintf(f, "FCW=%04x FSW=%04x [ST=%d] FTW=%02x MXCSR=%08x\n",

                    env->fpuc,

                    (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11,

                    env->fpstt,

                    fptag,

                    env->mxcsr);

        for(i=0;i<8;i++) {

#if defined(USE_X86LDOUBLE)

            union {

                long double d;

                struct {

                    uint64_t lower;

                    uint16_t upper;

                } l;

            } tmp;

            tmp.d = env->fpregs[i].d;

            cpu_fprintf(f, "FPR%d=%016" PRIx64 " %04x",

                        i, tmp.l.lower, tmp.l.upper);

#else

            cpu_fprintf(f, "FPR%d=%016" PRIx64,

                        i, env->fpregs[i].mmx.q);

#endif

            if ((i & 1) == 1)

                cpu_fprintf(f, "\n");

            else

                cpu_fprintf(f, " ");

        }

        if (env->hflags & HF_CS64_MASK)

            nb = 16;

        else

            nb = 8;

        for(i=0;i<nb;i++) {

            cpu_fprintf(f, "XMM%02d=%08x%08x%08x%08x",

                        i,

                        env->xmm_regs[i].XMM_L(3),

                        env->xmm_regs[i].XMM_L(2),

                        env->xmm_regs[i].XMM_L(1),

                        env->xmm_regs[i].XMM_L(0));

            if ((i & 1) == 1)

                cpu_fprintf(f, "\n");

            else

                cpu_fprintf(f, " ");

        }

    }

}

void FUNC_0(CPUState *VAR_0, FILE *VAR_3,

                    int (*VAR_2)(FILE *VAR_3, const char *VAR_3, ...),

                    int VAR_4)

{

    int VAR_5, VAR_6, VAR_7;

    char VAR_8[32];

    static const char *VAR_9[6] = { "ES", "CS", "SS", "DS", "FS", "GS" };



    if (kvm_enabled())

        kvm_arch_get_registers(VAR_0);



    VAR_5 = VAR_0->VAR_5;

#ifdef TARGET_X86_64

    if (VAR_0->hflags & HF_CS64_MASK) {

        VAR_2(VAR_3,

                    "RAX=%016" PRIx64 " RBX=%016" PRIx64 " RCX=%016" PRIx64 " RDX=%016" PRIx64 "\n"

                    "RSI=%016" PRIx64 " RDI=%016" PRIx64 " RBP=%016" PRIx64 " RSP=%016" PRIx64 "\n"

                    "R8 =%016" PRIx64 " R9 =%016" PRIx64 " R10=%016" PRIx64 " R11=%016" PRIx64 "\n"

                    "R12=%016" PRIx64 " R13=%016" PRIx64 " R14=%016" PRIx64 " R15=%016" PRIx64 "\n"

                    "RIP=%016" PRIx64 " RFL=%08x [%c%c%c%c%c%c%c] CPL=%d II=%d A20=%d SMM=%d HLT=%d\n",

                    VAR_0->regs[R_EAX],

                    VAR_0->regs[R_EBX],

                    VAR_0->regs[R_ECX],

                    VAR_0->regs[R_EDX],

                    VAR_0->regs[R_ESI],

                    VAR_0->regs[R_EDI],

                    VAR_0->regs[R_EBP],

                    VAR_0->regs[R_ESP],

                    VAR_0->regs[8],

                    VAR_0->regs[9],

                    VAR_0->regs[10],

                    VAR_0->regs[11],

                    VAR_0->regs[12],

                    VAR_0->regs[13],

                    VAR_0->regs[14],

                    VAR_0->regs[15],

                    VAR_0->eip, VAR_5,

                    VAR_5 & DF_MASK ? 'D' : '-',

                    VAR_5 & CC_O ? 'O' : '-',

                    VAR_5 & CC_S ? 'S' : '-',

                    VAR_5 & CC_Z ? 'Z' : '-',

                    VAR_5 & CC_A ? 'A' : '-',

                    VAR_5 & CC_P ? 'P' : '-',

                    VAR_5 & CC_C ? 'C' : '-',

                    VAR_0->hflags & HF_CPL_MASK,

                    (VAR_0->hflags >> HF_INHIBIT_IRQ_SHIFT) & 1,

                    (int)(VAR_0->a20_mask >> 20) & 1,

                    (VAR_0->hflags >> HF_SMM_SHIFT) & 1,

                    VAR_0->halted);

    } else

#endif

    {

        VAR_2(VAR_3, "EAX=%08x EBX=%08x ECX=%08x EDX=%08x\n"

                    "ESI=%08x EDI=%08x EBP=%08x ESP=%08x\n"

                    "EIP=%08x EFL=%08x [%c%c%c%c%c%c%c] CPL=%d II=%d A20=%d SMM=%d HLT=%d\n",

                    (uint32_t)VAR_0->regs[R_EAX],

                    (uint32_t)VAR_0->regs[R_EBX],

                    (uint32_t)VAR_0->regs[R_ECX],

                    (uint32_t)VAR_0->regs[R_EDX],

                    (uint32_t)VAR_0->regs[R_ESI],

                    (uint32_t)VAR_0->regs[R_EDI],

                    (uint32_t)VAR_0->regs[R_EBP],

                    (uint32_t)VAR_0->regs[R_ESP],

                    (uint32_t)VAR_0->eip, VAR_5,

                    VAR_5 & DF_MASK ? 'D' : '-',

                    VAR_5 & CC_O ? 'O' : '-',

                    VAR_5 & CC_S ? 'S' : '-',

                    VAR_5 & CC_Z ? 'Z' : '-',

                    VAR_5 & CC_A ? 'A' : '-',

                    VAR_5 & CC_P ? 'P' : '-',

                    VAR_5 & CC_C ? 'C' : '-',

                    VAR_0->hflags & HF_CPL_MASK,

                    (VAR_0->hflags >> HF_INHIBIT_IRQ_SHIFT) & 1,

                    (int)(VAR_0->a20_mask >> 20) & 1,

                    (VAR_0->hflags >> HF_SMM_SHIFT) & 1,

                    VAR_0->halted);

    }



    for(VAR_6 = 0; VAR_6 < 6; VAR_6++) {

        cpu_x86_dump_seg_cache(VAR_0, VAR_3, VAR_2, VAR_9[VAR_6],

                               &VAR_0->segs[VAR_6]);

    }

    cpu_x86_dump_seg_cache(VAR_0, VAR_3, VAR_2, "LDT", &VAR_0->ldt);

    cpu_x86_dump_seg_cache(VAR_0, VAR_3, VAR_2, "TR", &VAR_0->tr);



#ifdef TARGET_X86_64

    if (VAR_0->hflags & HF_LMA_MASK) {

        VAR_2(VAR_3, "GDT=     %016" PRIx64 " %08x\n",

                    VAR_0->gdt.base, VAR_0->gdt.limit);

        VAR_2(VAR_3, "IDT=     %016" PRIx64 " %08x\n",

                    VAR_0->idt.base, VAR_0->idt.limit);

        VAR_2(VAR_3, "CR0=%08x CR2=%016" PRIx64 " CR3=%016" PRIx64 " CR4=%08x\n",

                    (uint32_t)VAR_0->cr[0],

                    VAR_0->cr[2],

                    VAR_0->cr[3],

                    (uint32_t)VAR_0->cr[4]);

        for(VAR_6 = 0; VAR_6 < 4; VAR_6++)

            VAR_2(VAR_3, "DR%d=%016" PRIx64 " ", VAR_6, VAR_0->dr[VAR_6]);

        VAR_2(VAR_3, "\nDR6=%016" PRIx64 " DR7=%016" PRIx64 "\n",

                    VAR_0->dr[6], VAR_0->dr[7]);

    } else

#endif

    {

        VAR_2(VAR_3, "GDT=     %08x %08x\n",

                    (uint32_t)VAR_0->gdt.base, VAR_0->gdt.limit);

        VAR_2(VAR_3, "IDT=     %08x %08x\n",

                    (uint32_t)VAR_0->idt.base, VAR_0->idt.limit);

        VAR_2(VAR_3, "CR0=%08x CR2=%08x CR3=%08x CR4=%08x\n",

                    (uint32_t)VAR_0->cr[0],

                    (uint32_t)VAR_0->cr[2],

                    (uint32_t)VAR_0->cr[3],

                    (uint32_t)VAR_0->cr[4]);

        for(VAR_6 = 0; VAR_6 < 4; VAR_6++)

            VAR_2(VAR_3, "DR%d=%08x ", VAR_6, VAR_0->dr[VAR_6]);

        VAR_2(VAR_3, "\nDR6=%08x DR7=%08x\n", VAR_0->dr[6], VAR_0->dr[7]);

    }

    if (VAR_4 & X86_DUMP_CCOP) {

        if ((unsigned)VAR_0->cc_op < CC_OP_NB)

            snprintf(VAR_8, sizeof(VAR_8), "%s", cc_op_str[VAR_0->cc_op]);

        else

            snprintf(VAR_8, sizeof(VAR_8), "[%d]", VAR_0->cc_op);

#ifdef TARGET_X86_64

        if (VAR_0->hflags & HF_CS64_MASK) {

            VAR_2(VAR_3, "CCS=%016" PRIx64 " CCD=%016" PRIx64 " CCO=%-8s\n",

                        VAR_0->cc_src, VAR_0->cc_dst,

                        VAR_8);

        } else

#endif

        {

            VAR_2(VAR_3, "CCS=%08x CCD=%08x CCO=%-8s\n",

                        (uint32_t)VAR_0->cc_src, (uint32_t)VAR_0->cc_dst,

                        VAR_8);

        }

    }

    if (VAR_4 & X86_DUMP_FPU) {

        int VAR_10;

        VAR_10 = 0;

        for(VAR_6 = 0; VAR_6 < 8; VAR_6++) {

            VAR_10 |= ((!VAR_0->fptags[VAR_6]) << VAR_6);

        }

        VAR_2(VAR_3, "FCW=%04x FSW=%04x [ST=%d] FTW=%02x MXCSR=%08x\n",

                    VAR_0->fpuc,

                    (VAR_0->fpus & ~0x3800) | (VAR_0->fpstt & 0x7) << 11,

                    VAR_0->fpstt,

                    VAR_10,

                    VAR_0->mxcsr);

        for(VAR_6=0;VAR_6<8;VAR_6++) {

#if defined(USE_X86LDOUBLE)

            union {

                long double d;

                struct {

                    uint64_t lower;

                    uint16_t upper;

                } l;

            } tmp;

            tmp.d = VAR_0->fpregs[VAR_6].d;

            VAR_2(VAR_3, "FPR%d=%016" PRIx64 " %04x",

                        VAR_6, tmp.l.lower, tmp.l.upper);

#else

            VAR_2(VAR_3, "FPR%d=%016" PRIx64,

                        VAR_6, VAR_0->fpregs[VAR_6].mmx.q);

#endif

            if ((VAR_6 & 1) == 1)

                VAR_2(VAR_3, "\n");

            else

                VAR_2(VAR_3, " ");

        }

        if (VAR_0->hflags & HF_CS64_MASK)

            VAR_7 = 16;

        else

            VAR_7 = 8;

        for(VAR_6=0;VAR_6<VAR_7;VAR_6++) {

            VAR_2(VAR_3, "XMM%02d=%08x%08x%08x%08x",

                        VAR_6,

                        VAR_0->xmm_regs[VAR_6].XMM_L(3),

                        VAR_0->xmm_regs[VAR_6].XMM_L(2),

                        VAR_0->xmm_regs[VAR_6].XMM_L(1),

                        VAR_0->xmm_regs[VAR_6].XMM_L(0));

            if ((VAR_6 & 1) == 1)

                VAR_2(VAR_3, "\n");

            else

                VAR_2(VAR_3, " ");

        }

    }

}

void FUNC_0(CPUState *VAR_0, FILE *VAR_3,
int (*VAR_2)(FILE *VAR_3, const char *VAR_3, ...),
int VAR_4)
{ int VAR_5, VAR_6, VAR_7; char VAR_8[32]; static const char *VAR_9[6] = { "ES", "CS", "SS", "DS", "FS", "GS" }; if (kvm_enabled())
kvm_arch_get_registers(VAR_0); VAR_5 = VAR_0->VAR_5; #ifdef TARGET_X86_64
if (VAR_0->hflags & HF_CS64_MASK) { VAR_2(VAR_3,
"RAX=%016" PRIx64 " RBX=%016" PRIx64 " RCX=%016" PRIx64 " RDX=%016" PRIx64 "\n"
"RSI=%016" PRIx64 " RDI=%016" PRIx64 " RBP=%016" PRIx64 " RSP=%016" PRIx64 "\n"
"R8 =%016" PRIx64 " R9 =%016" PRIx64 " R10=%016" PRIx64 " R11=%016" PRIx64 "\n"
"R12=%016" PRIx64 " R13=%016" PRIx64 " R14=%016" PRIx64 " R15=%016" PRIx64 "\n"
"RIP=%016" PRIx64 " RFL=%08x [%c%c%c%c%c%c%c] CPL=%d II=%d A20=%d SMM=%d HLT=%d\n",
VAR_0->regs[R_EAX],
VAR_0->regs[R_EBX],
VAR_0->regs[R_ECX],
VAR_0->regs[R_EDX],
VAR_0->regs[R_ESI],
VAR_0->regs[R_EDI],
VAR_0->regs[R_EBP],
VAR_0->regs[R_ESP],
VAR_0->regs[8],
VAR_0->regs[9],
VAR_0->regs[10],
VAR_0->regs[11],
VAR_0->regs[12],
VAR_0->regs[13],
VAR_0->regs[14],
VAR_0->regs[15],
VAR_0->eip, VAR_5,
VAR_5 & DF_MASK ? 'D' : '-',
VAR_5 & CC_O ? 'O' : '-',
VAR_5 & CC_S ? 'S' : '-',
VAR_5 & CC_Z ? 'Z' : '-',
VAR_5 & CC_A ? 'A' : '-',
VAR_5 & CC_P ? 'P' : '-',
VAR_5 & CC_C ? 'C' : '-',
VAR_0->hflags & HF_CPL_MASK,
(VAR_0->hflags >> HF_INHIBIT_IRQ_SHIFT) & 1,
(int)(VAR_0->a20_mask >> 20) & 1,
(VAR_0->hflags >> HF_SMM_SHIFT) & 1,
VAR_0->halted); } else #endif
{ VAR_2(VAR_3, "EAX=%08x EBX=%08x ECX=%08x EDX=%08x\n"
"ESI=%08x EDI=%08x EBP=%08x ESP=%08x\n"
"EIP=%08x EFL=%08x [%c%c%c%c%c%c%c] CPL=%d II=%d A20=%d SMM=%d HLT=%d\n",
(uint32_t)VAR_0->regs[R_EAX],
(uint32_t)VAR_0->regs[R_EBX],
(uint32_t)VAR_0->regs[R_ECX],
(uint32_t)VAR_0->regs[R_EDX],
(uint32_t)VAR_0->regs[R_ESI],
(uint32_t)VAR_0->regs[R_EDI],
(uint32_t)VAR_0->regs[R_EBP],
(uint32_t)VAR_0->regs[R_ESP],
(uint32_t)VAR_0->eip, VAR_5,
VAR_5 & DF_MASK ? 'D' : '-',
VAR_5 & CC_O ? 'O' : '-',
VAR_5 & CC_S ? 'S' : '-',
VAR_5 & CC_Z ? 'Z' : '-',
VAR_5 & CC_A ? 'A' : '-',
VAR_5 & CC_P ? 'P' : '-',
VAR_5 & CC_C ? 'C' : '-',
VAR_0->hflags & HF_CPL_MASK,
(VAR_0->hflags >> HF_INHIBIT_IRQ_SHIFT) & 1,
(int)(VAR_0->a20_mask >> 20) & 1,
(VAR_0->hflags >> HF_SMM_SHIFT) & 1,
VAR_0->halted); } for(VAR_6 = 0; VAR_6 < 6; VAR_6++) { cpu_x86_dump_seg_cache(VAR_0, VAR_3, VAR_2, VAR_9[VAR_6],
&VAR_0->segs[VAR_6]); } cpu_x86_dump_seg_cache(VAR_0, VAR_3, VAR_2, "LDT", &VAR_0->ldt); cpu_x86_dump_seg_cache(VAR_0, VAR_3, VAR_2, "TR", &VAR_0->tr); #ifdef TARGET_X86_64
if (VAR_0->hflags & HF_LMA_MASK) { VAR_2(VAR_3, "GDT=     %016" PRIx64 " %08x\n",
VAR_0->gdt.base, VAR_0->gdt.limit); VAR_2(VAR_3, "IDT=     %016" PRIx64 " %08x\n",
VAR_0->idt.base, VAR_0->idt.limit); VAR_2(VAR_3, "CR0=%08x CR2=%016" PRIx64 " CR3=%016" PRIx64 " CR4=%08x\n",
(uint32_t)VAR_0->cr[0],
VAR_0->cr[2],
VAR_0->cr[3],
(uint32_t)VAR_0->cr[4]); for(VAR_6 = 0; VAR_6 < 4; VAR_6++) VAR_2(VAR_3, "DR%d=%016" PRIx64 " ", VAR_6, VAR_0->dr[VAR_6]); VAR_2(VAR_3, "\nDR6=%016" PRIx64 " DR7=%016" PRIx64 "\n",
VAR_0->dr[6], VAR_0->dr[7]); } else #endif
{ VAR_2(VAR_3, "GDT=     %08x %08x\n",
(uint32_t)VAR_0->gdt.base, VAR_0->gdt.limit); VAR_2(VAR_3, "IDT=     %08x %08x\n",
(uint32_t)VAR_0->idt.base, VAR_0->idt.limit); VAR_2(VAR_3, "CR0=%08x CR2=%08x CR3=%08x CR4=%08x\n",
(uint32_t)VAR_0->cr[0],
(uint32_t)VAR_0->cr[2],
(uint32_t)VAR_0->cr[3],
(uint32_t)VAR_0->cr[4]); for(VAR_6 = 0; VAR_6 < 4; VAR_6++) VAR_2(VAR_3, "DR%d=%08x ", VAR_6, VAR_0->dr[VAR_6]); VAR_2(VAR_3, "\nDR6=%08x DR7=%08x\n", VAR_0->dr[6], VAR_0->dr[7]); } if (VAR_4 & X86_DUMP_CCOP) { if ((unsigned)VAR_0->cc_op < CC_OP_NB)
snprintf(VAR_8, sizeof(VAR_8), "%s", cc_op_str[VAR_0->cc_op]); else
snprintf(VAR_8, sizeof(VAR_8), "[%d]", VAR_0->cc_op); #ifdef TARGET_X86_64
if (VAR_0->hflags & HF_CS64_MASK) { VAR_2(VAR_3, "CCS=%016" PRIx64 " CCD=%016" PRIx64 " CCO=%-8s\n",
VAR_0->cc_src, VAR_0->cc_dst,
VAR_8); } else #endif
{ VAR_2(VAR_3, "CCS=%08x CCD=%08x CCO=%-8s\n",
(uint32_t)VAR_0->cc_src, (uint32_t)VAR_0->cc_dst,
VAR_8); } } if (VAR_4 & X86_DUMP_FPU) { int VAR_10; VAR_10 = 0; for(VAR_6 = 0; VAR_6 < 8; VAR_6++) { VAR_10 |= ((!VAR_0->fptags[VAR_6]) << VAR_6); } VAR_2(VAR_3, "FCW=%04x FSW=%04x [ST=%d] FTW=%02x MXCSR=%08x\n",
VAR_0->fpuc,
(VAR_0->fpus & ~0x3800) | (VAR_0->fpstt & 0x7) << 11,
VAR_0->fpstt,
VAR_10,
VAR_0->mxcsr); for(VAR_6=0;VAR_6<8;VAR_6++) { #if defined(USE_X86LDOUBLE)
union { long double d; struct { uint64_t lower; uint16_t upper; } l; } tmp; tmp.d = VAR_0->fpregs[VAR_6].d; VAR_2(VAR_3, "FPR%d=%016" PRIx64 " %04x",
VAR_6, tmp.l.lower, tmp.l.upper); #else
VAR_2(VAR_3, "FPR%d=%016" PRIx64,
VAR_6, VAR_0->fpregs[VAR_6].mmx.q); #endif
if ((VAR_6 & 1) == 1)
VAR_2(VAR_3, "\n"); else
VAR_2(VAR_3, " "); } if (VAR_0->hflags & HF_CS64_MASK)
VAR_7 = 16; else
VAR_7 = 8; for(VAR_6=0;VAR_6<VAR_7;VAR_6++) { VAR_2(VAR_3, "XMM%02d=%08x%08x%08x%08x",
VAR_6,
VAR_0->xmm_regs[VAR_6].XMM_L(3),
VAR_0->xmm_regs[VAR_6].XMM_L(2),
VAR_0->xmm_regs[VAR_6].XMM_L(1),
VAR_0->xmm_regs[VAR_6].XMM_L(0)); if ((VAR_6 & 1) == 1)
VAR_2(VAR_3, "\n"); else
VAR_2(VAR_3, " "); } } }