static void mcf_intc_write(void *opaque, target_phys_addr_t addr,

                           uint64_t val, unsigned size)

{

    int offset;

    mcf_intc_state *s = (mcf_intc_state *)opaque;

    offset = addr & 0xff;

    if (offset >= 0x40 && offset < 0x80) {

        int n = offset - 0x40;

        s->icr[n] = val;

        if (val == 0)

            s->enabled &= ~(1ull << n);

        else

            s->enabled |= (1ull << n);

        mcf_intc_update(s);

        return;

    }

    switch (offset) {

    case 0x00: case 0x04:

        /* Ignore IPR writes.  */

        return;

    case 0x08:

        s->imr = (s->imr & 0xffffffff) | ((uint64_t)val << 32);

        break;

    case 0x0c:

        s->imr = (s->imr & 0xffffffff00000000ull) | (uint32_t)val;

        break;

    default:

        hw_error("mcf_intc_write: Bad write offset %d\n", offset);

        break;

    }

    mcf_intc_update(s);

}

static void mcf_intc_write(void *opaque, target_phys_addr_t addr,

                           uint64_t val, unsigned size)

{

    int offset;

    mcf_intc_state *s = (mcf_intc_state *)opaque;

    offset = addr & 0xff;

    if (offset >= 0x40 && offset < 0x80) {

        int n = offset - 0x40;

        s->icr[n] = val;

        if (val == 0)

            s->enabled &= ~(1ull << n);

        else

            s->enabled |= (1ull << n);

        mcf_intc_update(s);

        return;

    }

    switch (offset) {

    case 0x00: case 0x04:

        

        return;

    case 0x08:

        s->imr = (s->imr & 0xffffffff) | ((uint64_t)val << 32);

        break;

    case 0x0c:

        s->imr = (s->imr & 0xffffffff00000000ull) | (uint32_t)val;

        break;

    default:

        hw_error("mcf_intc_write: Bad write offset %d\n", offset);

        break;

    }

    mcf_intc_update(s);

}

static void FUNC_0(void *VAR_0, target_phys_addr_t VAR_1,

                           uint64_t VAR_2, unsigned VAR_3)

{

    int VAR_4;

    mcf_intc_state *s = (mcf_intc_state *)VAR_0;

    VAR_4 = VAR_1 & 0xff;

    if (VAR_4 >= 0x40 && VAR_4 < 0x80) {

        int VAR_5 = VAR_4 - 0x40;

        s->icr[VAR_5] = VAR_2;

        if (VAR_2 == 0)

            s->enabled &= ~(1ull << VAR_5);

        else

            s->enabled |= (1ull << VAR_5);

        mcf_intc_update(s);

        return;

    }

    switch (VAR_4) {

    case 0x00: case 0x04:

        

        return;

    case 0x08:

        s->imr = (s->imr & 0xffffffff) | ((uint64_t)VAR_2 << 32);

        break;

    case 0x0c:

        s->imr = (s->imr & 0xffffffff00000000ull) | (uint32_t)VAR_2;

        break;

    default:

        hw_error("FUNC_0: Bad write VAR_4 %d\VAR_5", VAR_4);

        break;

    }

    mcf_intc_update(s);

}

static void FUNC_0(void *VAR_0, target_phys_addr_t VAR_1,
uint64_t VAR_2, unsigned VAR_3)
{ int VAR_4; mcf_intc_state *s = (mcf_intc_state *)VAR_0; VAR_4 = VAR_1 & 0xff; if (VAR_4 >= 0x40 && VAR_4 < 0x80) { int VAR_5 = VAR_4 - 0x40; s->icr[VAR_5] = VAR_2; if (VAR_2 == 0)
s->enabled &= ~(1ull << VAR_5); else
s->enabled |= (1ull << VAR_5); mcf_intc_update(s); return; } switch (VAR_4) { case 0x00: case 0x04:
return; case 0x08:
s->imr = (s->imr & 0xffffffff) | ((uint64_t)VAR_2 << 32); break; case 0x0c:
s->imr = (s->imr & 0xffffffff00000000ull) | (uint32_t)VAR_2; break; default:
hw_error("FUNC_0: Bad write VAR_4 %d\VAR_5", VAR_4); break; } mcf_intc_update(s); }