xilinx_axienet_data_stream_push(StreamSlave *obj, uint8_t *buf, size_t size,

                                uint32_t *hdr)

{

    XilinxAXIEnetStreamSlave *ds = XILINX_AXI_ENET_DATA_STREAM(obj);

    XilinxAXIEnet *s = ds->enet;



    /* TX enable ?  */

    if (!(s->tc & TC_TX)) {

        return size;

    }



    /* Jumbo or vlan sizes ?  */

    if (!(s->tc & TC_JUM)) {

        if (size > 1518 && size <= 1522 && !(s->tc & TC_VLAN)) {

            return size;

        }

    }



    if (hdr[0] & 1) {

        unsigned int start_off = hdr[1] >> 16;

        unsigned int write_off = hdr[1] & 0xffff;

        uint32_t tmp_csum;

        uint16_t csum;



        tmp_csum = net_checksum_add(size - start_off,

                                    (uint8_t *)buf + start_off);

        /* Accumulate the seed.  */

        tmp_csum += hdr[2] & 0xffff;



        /* Fold the 32bit partial checksum.  */

        csum = net_checksum_finish(tmp_csum);



        /* Writeback.  */

        buf[write_off] = csum >> 8;

        buf[write_off + 1] = csum & 0xff;

    }



    qemu_send_packet(qemu_get_queue(s->nic), buf, size);



    s->stats.tx_bytes += size;

    s->regs[R_IS] |= IS_TX_COMPLETE;

    enet_update_irq(s);



    return size;

}

xilinx_axienet_data_stream_push(StreamSlave *obj, uint8_t *buf, size_t size,

                                uint32_t *hdr)

{

    XilinxAXIEnetStreamSlave *ds = XILINX_AXI_ENET_DATA_STREAM(obj);

    XilinxAXIEnet *s = ds->enet;



    

    if (!(s->tc & TC_TX)) {

        return size;

    }



    

    if (!(s->tc & TC_JUM)) {

        if (size > 1518 && size <= 1522 && !(s->tc & TC_VLAN)) {

            return size;

        }

    }



    if (hdr[0] & 1) {

        unsigned int start_off = hdr[1] >> 16;

        unsigned int write_off = hdr[1] & 0xffff;

        uint32_t tmp_csum;

        uint16_t csum;



        tmp_csum = net_checksum_add(size - start_off,

                                    (uint8_t *)buf + start_off);

        

        tmp_csum += hdr[2] & 0xffff;



        

        csum = net_checksum_finish(tmp_csum);



        

        buf[write_off] = csum >> 8;

        buf[write_off + 1] = csum & 0xff;

    }



    qemu_send_packet(qemu_get_queue(s->nic), buf, size);



    s->stats.tx_bytes += size;

    s->regs[R_IS] |= IS_TX_COMPLETE;

    enet_update_irq(s);



    return size;

}

FUNC_0(StreamSlave *VAR_0, uint8_t *VAR_1, size_t VAR_2,

                                uint32_t *VAR_3)

{

    XilinxAXIEnetStreamSlave *ds = XILINX_AXI_ENET_DATA_STREAM(VAR_0);

    XilinxAXIEnet *s = ds->enet;



    

    if (!(s->tc & TC_TX)) {

        return VAR_2;

    }



    

    if (!(s->tc & TC_JUM)) {

        if (VAR_2 > 1518 && VAR_2 <= 1522 && !(s->tc & TC_VLAN)) {

            return VAR_2;

        }

    }



    if (VAR_3[0] & 1) {

        unsigned int VAR_4 = VAR_3[1] >> 16;

        unsigned int VAR_5 = VAR_3[1] & 0xffff;

        uint32_t tmp_csum;

        uint16_t csum;



        tmp_csum = net_checksum_add(VAR_2 - VAR_4,

                                    (uint8_t *)VAR_1 + VAR_4);

        

        tmp_csum += VAR_3[2] & 0xffff;



        

        csum = net_checksum_finish(tmp_csum);



        

        VAR_1[VAR_5] = csum >> 8;

        VAR_1[VAR_5 + 1] = csum & 0xff;

    }



    qemu_send_packet(qemu_get_queue(s->nic), VAR_1, VAR_2);



    s->stats.tx_bytes += VAR_2;

    s->regs[R_IS] |= IS_TX_COMPLETE;

    enet_update_irq(s);



    return VAR_2;

}

FUNC_0(StreamSlave *VAR_0, uint8_t *VAR_1, size_t VAR_2,
uint32_t *VAR_3)
{ XilinxAXIEnetStreamSlave *ds = XILINX_AXI_ENET_DATA_STREAM(VAR_0); XilinxAXIEnet *s = ds->enet; if (!(s->tc & TC_TX)) { return VAR_2; } if (!(s->tc & TC_JUM)) { if (VAR_2 > 1518 && VAR_2 <= 1522 && !(s->tc & TC_VLAN)) { return VAR_2; } } if (VAR_3[0] & 1) { unsigned int VAR_4 = VAR_3[1] >> 16; unsigned int VAR_5 = VAR_3[1] & 0xffff; uint32_t tmp_csum; uint16_t csum; tmp_csum = net_checksum_add(VAR_2 - VAR_4,
(uint8_t *)VAR_1 + VAR_4); tmp_csum += VAR_3[2] & 0xffff; csum = net_checksum_finish(tmp_csum); VAR_1[VAR_5] = csum >> 8; VAR_1[VAR_5 + 1] = csum & 0xff; } qemu_send_packet(qemu_get_queue(s->nic), VAR_1, VAR_2); s->stats.tx_bytes += VAR_2; s->regs[R_IS] |= IS_TX_COMPLETE; enet_update_irq(s); return VAR_2; }