static void vt82c686b_write_config(PCIDevice * d, uint32_t address,

                                   uint32_t val, int len)

{

    VT82C686BState *vt686 = DO_UPCAST(VT82C686BState, dev, d);



    DPRINTF("vt82c686b_write_config  address 0x%x  val 0x%x len 0x%x \n",

           address, val, len);



    pci_default_write_config(d, address, val, len);

    if (address == 0x85) {  /* enable or disable super IO configure */

        if (val & 0x2) {

            /* floppy also uses 0x3f0 and 0x3f1.

             * But we do not emulate flopy,so just set it here. */

            isa_unassign_ioport(0x3f0, 2);

            register_ioport_read(0x3f0, 2, 1, superio_ioport_readb,

                                 &vt686->superio_conf);

            register_ioport_write(0x3f0, 2, 1, superio_ioport_writeb,

                                  &vt686->superio_conf);

        } else {

            isa_unassign_ioport(0x3f0, 2);

        }

    }

}

static void vt82c686b_write_config(PCIDevice * d, uint32_t address,

                                   uint32_t val, int len)

{

    VT82C686BState *vt686 = DO_UPCAST(VT82C686BState, dev, d);



    DPRINTF("vt82c686b_write_config  address 0x%x  val 0x%x len 0x%x \n",

           address, val, len);



    pci_default_write_config(d, address, val, len);

    if (address == 0x85) {  

        if (val & 0x2) {

            



            isa_unassign_ioport(0x3f0, 2);

            register_ioport_read(0x3f0, 2, 1, superio_ioport_readb,

                                 &vt686->superio_conf);

            register_ioport_write(0x3f0, 2, 1, superio_ioport_writeb,

                                  &vt686->superio_conf);

        } else {

            isa_unassign_ioport(0x3f0, 2);

        }

    }

}

static void FUNC_0(PCIDevice * VAR_0, uint32_t VAR_1,

                                   uint32_t VAR_2, int VAR_3)

{

    VT82C686BState *vt686 = DO_UPCAST(VT82C686BState, dev, VAR_0);



    DPRINTF("FUNC_0  VAR_1 0x%x  VAR_2 0x%x VAR_3 0x%x \n",

           VAR_1, VAR_2, VAR_3);



    pci_default_write_config(VAR_0, VAR_1, VAR_2, VAR_3);

    if (VAR_1 == 0x85) {  

        if (VAR_2 & 0x2) {

            



            isa_unassign_ioport(0x3f0, 2);

            register_ioport_read(0x3f0, 2, 1, superio_ioport_readb,

                                 &vt686->superio_conf);

            register_ioport_write(0x3f0, 2, 1, superio_ioport_writeb,

                                  &vt686->superio_conf);

        } else {

            isa_unassign_ioport(0x3f0, 2);

        }

    }

}

static void FUNC_0(PCIDevice * VAR_0, uint32_t VAR_1,
uint32_t VAR_2, int VAR_3)
{ VT82C686BState *vt686 = DO_UPCAST(VT82C686BState, dev, VAR_0); DPRINTF("FUNC_0  VAR_1 0x%x  VAR_2 0x%x VAR_3 0x%x \n",
VAR_1, VAR_2, VAR_3); pci_default_write_config(VAR_0, VAR_1, VAR_2, VAR_3); if (VAR_1 == 0x85) { if (VAR_2 & 0x2) { isa_unassign_ioport(0x3f0, 2); register_ioport_read(0x3f0, 2, 1, superio_ioport_readb,
&vt686->superio_conf); register_ioport_write(0x3f0, 2, 1, superio_ioport_writeb,
&vt686->superio_conf); } else { isa_unassign_ioport(0x3f0, 2); } } }