int ppc_hash64_handle_mmu_fault(CPUPPCState *env, target_ulong address, int rw,

                                int mmu_idx)

{

    struct mmu_ctx_hash64 ctx;

    int access_type;

    int ret = 0;



    if (rw == 2) {

        /* code access */

        rw = 0;

        access_type = ACCESS_CODE;

    } else {

        /* data access */

        access_type = env->access_type;

    }

    ret = ppc_hash64_get_physical_address(env, &ctx, address, rw, access_type);

    if (ret == 0) {

        tlb_set_page(env, address & TARGET_PAGE_MASK,

                     ctx.raddr & TARGET_PAGE_MASK, ctx.prot,

                     mmu_idx, TARGET_PAGE_SIZE);

        ret = 0;

    } else if (ret < 0) {

        LOG_MMU_STATE(env);

        if (access_type == ACCESS_CODE) {

            switch (ret) {

            case -1:

                env->exception_index = POWERPC_EXCP_ISI;

                env->error_code = 0x40000000;

                break;

            case -2:

                /* Access rights violation */

                env->exception_index = POWERPC_EXCP_ISI;

                env->error_code = 0x08000000;

                break;

            case -3:

                /* No execute protection violation */

                env->exception_index = POWERPC_EXCP_ISI;

                env->error_code = 0x10000000;

                break;

            case -5:

                /* No match in segment table */

                env->exception_index = POWERPC_EXCP_ISEG;

                env->error_code = 0;

                break;

            }

        } else {

            switch (ret) {

            case -1:

                /* No matches in page tables or TLB */

                env->exception_index = POWERPC_EXCP_DSI;

                env->error_code = 0;

                env->spr[SPR_DAR] = address;

                if (rw == 1) {

                    env->spr[SPR_DSISR] = 0x42000000;

                } else {

                    env->spr[SPR_DSISR] = 0x40000000;

                }

                break;

            case -2:

                /* Access rights violation */

                env->exception_index = POWERPC_EXCP_DSI;

                env->error_code = 0;

                env->spr[SPR_DAR] = address;

                if (rw == 1) {

                    env->spr[SPR_DSISR] = 0x0A000000;

                } else {

                    env->spr[SPR_DSISR] = 0x08000000;

                }

                break;

            case -5:

                /* No match in segment table */

                env->exception_index = POWERPC_EXCP_DSEG;

                env->error_code = 0;

                env->spr[SPR_DAR] = address;

                break;

            }

        }

#if 0

        printf("%s: set exception to %d %02x\n", __func__,

               env->exception, env->error_code);

#endif

        ret = 1;

    }



    return ret;

}

int ppc_hash64_handle_mmu_fault(CPUPPCState *env, target_ulong address, int rw,

                                int mmu_idx)

{

    struct mmu_ctx_hash64 ctx;

    int access_type;

    int ret = 0;



    if (rw == 2) {

        

        rw = 0;

        access_type = ACCESS_CODE;

    } else {

        

        access_type = env->access_type;

    }

    ret = ppc_hash64_get_physical_address(env, &ctx, address, rw, access_type);

    if (ret == 0) {

        tlb_set_page(env, address & TARGET_PAGE_MASK,

                     ctx.raddr & TARGET_PAGE_MASK, ctx.prot,

                     mmu_idx, TARGET_PAGE_SIZE);

        ret = 0;

    } else if (ret < 0) {

        LOG_MMU_STATE(env);

        if (access_type == ACCESS_CODE) {

            switch (ret) {

            case -1:

                env->exception_index = POWERPC_EXCP_ISI;

                env->error_code = 0x40000000;

                break;

            case -2:

                

                env->exception_index = POWERPC_EXCP_ISI;

                env->error_code = 0x08000000;

                break;

            case -3:

                

                env->exception_index = POWERPC_EXCP_ISI;

                env->error_code = 0x10000000;

                break;

            case -5:

                

                env->exception_index = POWERPC_EXCP_ISEG;

                env->error_code = 0;

                break;

            }

        } else {

            switch (ret) {

            case -1:

                

                env->exception_index = POWERPC_EXCP_DSI;

                env->error_code = 0;

                env->spr[SPR_DAR] = address;

                if (rw == 1) {

                    env->spr[SPR_DSISR] = 0x42000000;

                } else {

                    env->spr[SPR_DSISR] = 0x40000000;

                }

                break;

            case -2:

                

                env->exception_index = POWERPC_EXCP_DSI;

                env->error_code = 0;

                env->spr[SPR_DAR] = address;

                if (rw == 1) {

                    env->spr[SPR_DSISR] = 0x0A000000;

                } else {

                    env->spr[SPR_DSISR] = 0x08000000;

                }

                break;

            case -5:

                

                env->exception_index = POWERPC_EXCP_DSEG;

                env->error_code = 0;

                env->spr[SPR_DAR] = address;

                break;

            }

        }

#if 0

        printf("%s: set exception to %d %02x\n", __func__,

               env->exception, env->error_code);

#endif

        ret = 1;

    }



    return ret;

}

int FUNC_0(CPUPPCState *VAR_0, target_ulong VAR_1, int VAR_2,

                                int VAR_3)

{

    struct mmu_ctx_hash64 VAR_4;

    int VAR_5;

    int VAR_6 = 0;



    if (VAR_2 == 2) {

        

        VAR_2 = 0;

        VAR_5 = ACCESS_CODE;

    } else {

        

        VAR_5 = VAR_0->VAR_5;

    }

    VAR_6 = ppc_hash64_get_physical_address(VAR_0, &VAR_4, VAR_1, VAR_2, VAR_5);

    if (VAR_6 == 0) {

        tlb_set_page(VAR_0, VAR_1 & TARGET_PAGE_MASK,

                     VAR_4.raddr & TARGET_PAGE_MASK, VAR_4.prot,

                     VAR_3, TARGET_PAGE_SIZE);

        VAR_6 = 0;

    } else if (VAR_6 < 0) {

        LOG_MMU_STATE(VAR_0);

        if (VAR_5 == ACCESS_CODE) {

            switch (VAR_6) {

            case -1:

                VAR_0->exception_index = POWERPC_EXCP_ISI;

                VAR_0->error_code = 0x40000000;

                break;

            case -2:

                

                VAR_0->exception_index = POWERPC_EXCP_ISI;

                VAR_0->error_code = 0x08000000;

                break;

            case -3:

                

                VAR_0->exception_index = POWERPC_EXCP_ISI;

                VAR_0->error_code = 0x10000000;

                break;

            case -5:

                

                VAR_0->exception_index = POWERPC_EXCP_ISEG;

                VAR_0->error_code = 0;

                break;

            }

        } else {

            switch (VAR_6) {

            case -1:

                

                VAR_0->exception_index = POWERPC_EXCP_DSI;

                VAR_0->error_code = 0;

                VAR_0->spr[SPR_DAR] = VAR_1;

                if (VAR_2 == 1) {

                    VAR_0->spr[SPR_DSISR] = 0x42000000;

                } else {

                    VAR_0->spr[SPR_DSISR] = 0x40000000;

                }

                break;

            case -2:

                

                VAR_0->exception_index = POWERPC_EXCP_DSI;

                VAR_0->error_code = 0;

                VAR_0->spr[SPR_DAR] = VAR_1;

                if (VAR_2 == 1) {

                    VAR_0->spr[SPR_DSISR] = 0x0A000000;

                } else {

                    VAR_0->spr[SPR_DSISR] = 0x08000000;

                }

                break;

            case -5:

                

                VAR_0->exception_index = POWERPC_EXCP_DSEG;

                VAR_0->error_code = 0;

                VAR_0->spr[SPR_DAR] = VAR_1;

                break;

            }

        }

#if 0

        printf("%s: set exception to %d %02x\n", __func__,

               VAR_0->exception, VAR_0->error_code);

#endif

        VAR_6 = 1;

    }



    return VAR_6;

}

int FUNC_0(CPUPPCState *VAR_0, target_ulong VAR_1, int VAR_2,
int VAR_3)
{ struct mmu_ctx_hash64 VAR_4; int VAR_5; int VAR_6 = 0; if (VAR_2 == 2) { VAR_2 = 0; VAR_5 = ACCESS_CODE; } else { VAR_5 = VAR_0->VAR_5; } VAR_6 = ppc_hash64_get_physical_address(VAR_0, &VAR_4, VAR_1, VAR_2, VAR_5); if (VAR_6 == 0) { tlb_set_page(VAR_0, VAR_1 & TARGET_PAGE_MASK,
VAR_4.raddr & TARGET_PAGE_MASK, VAR_4.prot,
VAR_3, TARGET_PAGE_SIZE); VAR_6 = 0; } else if (VAR_6 < 0) { LOG_MMU_STATE(VAR_0); if (VAR_5 == ACCESS_CODE) { switch (VAR_6) { case -1:
VAR_0->exception_index = POWERPC_EXCP_ISI; VAR_0->error_code = 0x40000000; break; case -2:
VAR_0->exception_index = POWERPC_EXCP_ISI; VAR_0->error_code = 0x08000000; break; case -3:
VAR_0->exception_index = POWERPC_EXCP_ISI; VAR_0->error_code = 0x10000000; break; case -5:
VAR_0->exception_index = POWERPC_EXCP_ISEG; VAR_0->error_code = 0; break; } } else { switch (VAR_6) { case -1:
VAR_0->exception_index = POWERPC_EXCP_DSI; VAR_0->error_code = 0; VAR_0->spr[SPR_DAR] = VAR_1; if (VAR_2 == 1) { VAR_0->spr[SPR_DSISR] = 0x42000000; } else { VAR_0->spr[SPR_DSISR] = 0x40000000; } break; case -2:
VAR_0->exception_index = POWERPC_EXCP_DSI; VAR_0->error_code = 0; VAR_0->spr[SPR_DAR] = VAR_1; if (VAR_2 == 1) { VAR_0->spr[SPR_DSISR] = 0x0A000000; } else { VAR_0->spr[SPR_DSISR] = 0x08000000; } break; case -5:
VAR_0->exception_index = POWERPC_EXCP_DSEG; VAR_0->error_code = 0; VAR_0->spr[SPR_DAR] = VAR_1; break; } } #if 0
printf("%s: set exception to %d %02x\n", __func__,
VAR_0->exception, VAR_0->error_code); #endif
VAR_6 = 1; } return VAR_6; }