static void check_cmd(AHCIState *s, int port)

{

    AHCIPortRegs *pr = &s->dev[port].port_regs;

    int slot;



    if ((pr->cmd & PORT_CMD_START) && pr->cmd_issue) {

        for (slot = 0; (slot < 32) && pr->cmd_issue; slot++) {

            if ((pr->cmd_issue & (1 << slot)) &&

                !handle_cmd(s, port, slot)) {

                pr->cmd_issue &= ~(1 << slot);

            }

        }

    }

}

static void check_cmd(AHCIState *s, int port)

{

    AHCIPortRegs *pr = &s->dev[port].port_regs;

    int slot;



    if ((pr->cmd & PORT_CMD_START) && pr->cmd_issue) {

        for (slot = 0; (slot < 32) && pr->cmd_issue; slot++) {

            if ((pr->cmd_issue & (1 << slot)) &&

                !handle_cmd(s, port, slot)) {

                pr->cmd_issue &= ~(1 << slot);

            }

        }

    }

}

            if ((pr->cmd_issue & (1 << slot)) &&                 pr->cmd_issue &= ~(1 << slot);
static void FUNC_0(AHCIState *VAR_0, int VAR_1)

{

    AHCIPortRegs *pr = &VAR_0->dev[VAR_1].port_regs;

    int VAR_2;



    if ((pr->cmd & PORT_CMD_START) && pr->cmd_issue) {

        for (VAR_2 = 0; (VAR_2 < 32) && pr->cmd_issue; VAR_2++) {

            if ((pr->cmd_issue & (1 << VAR_2)) &&

                !handle_cmd(VAR_0, VAR_1, VAR_2)) {

                pr->cmd_issue &= ~(1 << VAR_2);

            }

        }

    }

}

static void FUNC_0(AHCIState *VAR_0, int VAR_1)
{ AHCIPortRegs *pr = &VAR_0->dev[VAR_1].port_regs; int VAR_2; if ((pr->cmd & PORT_CMD_START) && pr->cmd_issue) { for (VAR_2 = 0; (VAR_2 < 32) && pr->cmd_issue; VAR_2++) { if ((pr->cmd_issue & (1 << VAR_2)) &&
!handle_cmd(VAR_0, VAR_1, VAR_2)) { pr->cmd_issue &= ~(1 << VAR_2); } } } }