static void cadence_timer_sync(CadenceTimerState *s)

{

    int i;

    int64_t r, x;

    int64_t interval = ((s->reg_count & COUNTER_CTRL_INT) ?

            (int64_t)s->reg_interval + 1 : 0x10000ULL) << 16;

    uint64_t old_time = s->cpu_time;



    s->cpu_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);

    DB_PRINT("cpu time: %lld ns\n", (long long)old_time);



    if (!s->cpu_time_valid || old_time == s->cpu_time) {

        s->cpu_time_valid = 1;

        return;

    }



    r = (int64_t)cadence_timer_get_steps(s, s->cpu_time - old_time);

    x = (int64_t)s->reg_value + ((s->reg_count & COUNTER_CTRL_DEC) ? -r : r);



    for (i = 0; i < 3; ++i) {

        int64_t m = (int64_t)s->reg_match[i] << 16;

        if (m > interval) {

            continue;

        }

        /* check to see if match event has occurred. check m +/- interval

         * to account for match events in wrap around cases */

        if (is_between(m, s->reg_value, x) ||

            is_between(m + interval, s->reg_value, x) ||

            is_between(m - interval, s->reg_value, x)) {

            s->reg_intr |= (2 << i);

        }

    }

    while (x < 0) {

        x += interval;

    }

    s->reg_value = (uint32_t)(x % interval);



    if (s->reg_value != x) {

        s->reg_intr |= (s->reg_count & COUNTER_CTRL_INT) ?

            COUNTER_INTR_IV : COUNTER_INTR_OV;

    }

    cadence_timer_update(s);

}

static void cadence_timer_sync(CadenceTimerState *s)

{

    int i;

    int64_t r, x;

    int64_t interval = ((s->reg_count & COUNTER_CTRL_INT) ?

            (int64_t)s->reg_interval + 1 : 0x10000ULL) << 16;

    uint64_t old_time = s->cpu_time;



    s->cpu_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);

    DB_PRINT("cpu time: %lld ns\n", (long long)old_time);



    if (!s->cpu_time_valid || old_time == s->cpu_time) {

        s->cpu_time_valid = 1;

        return;

    }



    r = (int64_t)cadence_timer_get_steps(s, s->cpu_time - old_time);

    x = (int64_t)s->reg_value + ((s->reg_count & COUNTER_CTRL_DEC) ? -r : r);



    for (i = 0; i < 3; ++i) {

        int64_t m = (int64_t)s->reg_match[i] << 16;

        if (m > interval) {

            continue;

        }

        



        if (is_between(m, s->reg_value, x) ||

            is_between(m + interval, s->reg_value, x) ||

            is_between(m - interval, s->reg_value, x)) {

            s->reg_intr |= (2 << i);

        }

    }

    while (x < 0) {

        x += interval;

    }

    s->reg_value = (uint32_t)(x % interval);



    if (s->reg_value != x) {

        s->reg_intr |= (s->reg_count & COUNTER_CTRL_INT) ?

            COUNTER_INTR_IV : COUNTER_INTR_OV;

    }

    cadence_timer_update(s);

}

static void FUNC_0(CadenceTimerState *VAR_0)

{

    int VAR_1;

    int64_t r, x;

    int64_t interval = ((VAR_0->reg_count & COUNTER_CTRL_INT) ?

            (int64_t)VAR_0->reg_interval + 1 : 0x10000ULL) << 16;

    uint64_t old_time = VAR_0->cpu_time;



    VAR_0->cpu_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);

    DB_PRINT("cpu time: %lld ns\n", (long long)old_time);



    if (!VAR_0->cpu_time_valid || old_time == VAR_0->cpu_time) {

        VAR_0->cpu_time_valid = 1;

        return;

    }



    r = (int64_t)cadence_timer_get_steps(VAR_0, VAR_0->cpu_time - old_time);

    x = (int64_t)VAR_0->reg_value + ((VAR_0->reg_count & COUNTER_CTRL_DEC) ? -r : r);



    for (VAR_1 = 0; VAR_1 < 3; ++VAR_1) {

        int64_t m = (int64_t)VAR_0->reg_match[VAR_1] << 16;

        if (m > interval) {

            continue;

        }

        



        if (is_between(m, VAR_0->reg_value, x) ||

            is_between(m + interval, VAR_0->reg_value, x) ||

            is_between(m - interval, VAR_0->reg_value, x)) {

            VAR_0->reg_intr |= (2 << VAR_1);

        }

    }

    while (x < 0) {

        x += interval;

    }

    VAR_0->reg_value = (uint32_t)(x % interval);



    if (VAR_0->reg_value != x) {

        VAR_0->reg_intr |= (VAR_0->reg_count & COUNTER_CTRL_INT) ?

            COUNTER_INTR_IV : COUNTER_INTR_OV;

    }

    cadence_timer_update(VAR_0);

}

static void FUNC_0(CadenceTimerState *VAR_0)
{ int VAR_1; int64_t r, x; int64_t interval = ((VAR_0->reg_count & COUNTER_CTRL_INT) ?
(int64_t)VAR_0->reg_interval + 1 : 0x10000ULL) << 16; uint64_t old_time = VAR_0->cpu_time; VAR_0->cpu_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); DB_PRINT("cpu time: %lld ns\n", (long long)old_time); if (!VAR_0->cpu_time_valid || old_time == VAR_0->cpu_time) { VAR_0->cpu_time_valid = 1; return; } r = (int64_t)cadence_timer_get_steps(VAR_0, VAR_0->cpu_time - old_time); x = (int64_t)VAR_0->reg_value + ((VAR_0->reg_count & COUNTER_CTRL_DEC) ? -r : r); for (VAR_1 = 0; VAR_1 < 3; ++VAR_1) { int64_t m = (int64_t)VAR_0->reg_match[VAR_1] << 16; if (m > interval) { continue; } if (is_between(m, VAR_0->reg_value, x) ||
is_between(m + interval, VAR_0->reg_value, x) ||
is_between(m - interval, VAR_0->reg_value, x)) { VAR_0->reg_intr |= (2 << VAR_1); } } while (x < 0) { x += interval; } VAR_0->reg_value = (uint32_t)(x % interval); if (VAR_0->reg_value != x) { VAR_0->reg_intr |= (VAR_0->reg_count & COUNTER_CTRL_INT) ?
COUNTER_INTR_IV : COUNTER_INTR_OV; } cadence_timer_update(VAR_0); }