void cpu_save(QEMUFile *f, void *opaque)

{

    CPUState *env = (CPUState *)opaque;

    unsigned int i, j;



    cpu_synchronize_state(env);



    for (i = 0; i < 32; i++)

        qemu_put_betls(f, &env->gpr[i]);

#if !defined(TARGET_PPC64)

    for (i = 0; i < 32; i++)

        qemu_put_betls(f, &env->gprh[i]);

#endif

    qemu_put_betls(f, &env->lr);

    qemu_put_betls(f, &env->ctr);

    for (i = 0; i < 8; i++)

        qemu_put_be32s(f, &env->crf[i]);

    qemu_put_betls(f, &env->xer);

    qemu_put_betls(f, &env->reserve_addr);

    qemu_put_betls(f, &env->msr);

    for (i = 0; i < 4; i++)

        qemu_put_betls(f, &env->tgpr[i]);

    for (i = 0; i < 32; i++) {

        union {

            float64 d;

            uint64_t l;

        } u;

        u.d = env->fpr[i];

        qemu_put_be64(f, u.l);

    }

    qemu_put_be32s(f, &env->fpscr);

    qemu_put_sbe32s(f, &env->access_type);

#if !defined(CONFIG_USER_ONLY)

#if defined(TARGET_PPC64)

    qemu_put_betls(f, &env->asr);

    qemu_put_sbe32s(f, &env->slb_nr);

#endif

    qemu_put_betls(f, &env->sdr1);

    for (i = 0; i < 32; i++)

        qemu_put_betls(f, &env->sr[i]);

    for (i = 0; i < 2; i++)

        for (j = 0; j < 8; j++)

            qemu_put_betls(f, &env->DBAT[i][j]);

    for (i = 0; i < 2; i++)

        for (j = 0; j < 8; j++)

            qemu_put_betls(f, &env->IBAT[i][j]);

    qemu_put_sbe32s(f, &env->nb_tlb);

    qemu_put_sbe32s(f, &env->tlb_per_way);

    qemu_put_sbe32s(f, &env->nb_ways);

    qemu_put_sbe32s(f, &env->last_way);

    qemu_put_sbe32s(f, &env->id_tlbs);

    qemu_put_sbe32s(f, &env->nb_pids);

    if (env->tlb) {

        // XXX assumes 6xx

        for (i = 0; i < env->nb_tlb; i++) {

            qemu_put_betls(f, &env->tlb[i].tlb6.pte0);

            qemu_put_betls(f, &env->tlb[i].tlb6.pte1);

            qemu_put_betls(f, &env->tlb[i].tlb6.EPN);

        }

    }

    for (i = 0; i < 4; i++)

        qemu_put_betls(f, &env->pb[i]);

#endif

    for (i = 0; i < 1024; i++)

        qemu_put_betls(f, &env->spr[i]);

    qemu_put_be32s(f, &env->vscr);

    qemu_put_be64s(f, &env->spe_acc);

    qemu_put_be32s(f, &env->spe_fscr);

    qemu_put_betls(f, &env->msr_mask);

    qemu_put_be32s(f, &env->flags);

    qemu_put_sbe32s(f, &env->error_code);

    qemu_put_be32s(f, &env->pending_interrupts);

#if !defined(CONFIG_USER_ONLY)

    qemu_put_be32s(f, &env->irq_input_state);

    for (i = 0; i < POWERPC_EXCP_NB; i++)

        qemu_put_betls(f, &env->excp_vectors[i]);

    qemu_put_betls(f, &env->excp_prefix);

    qemu_put_betls(f, &env->hreset_excp_prefix);

    qemu_put_betls(f, &env->ivor_mask);

    qemu_put_betls(f, &env->ivpr_mask);

    qemu_put_betls(f, &env->hreset_vector);

#endif

    qemu_put_betls(f, &env->nip);

    qemu_put_betls(f, &env->hflags);

    qemu_put_betls(f, &env->hflags_nmsr);

    qemu_put_sbe32s(f, &env->mmu_idx);

    qemu_put_sbe32s(f, &env->power_mode);

}

void cpu_save(QEMUFile *f, void *opaque)

{

    CPUState *env = (CPUState *)opaque;

    unsigned int i, j;



    cpu_synchronize_state(env);



    for (i = 0; i < 32; i++)

        qemu_put_betls(f, &env->gpr[i]);

#if !defined(TARGET_PPC64)

    for (i = 0; i < 32; i++)

        qemu_put_betls(f, &env->gprh[i]);

#endif

    qemu_put_betls(f, &env->lr);

    qemu_put_betls(f, &env->ctr);

    for (i = 0; i < 8; i++)

        qemu_put_be32s(f, &env->crf[i]);

    qemu_put_betls(f, &env->xer);

    qemu_put_betls(f, &env->reserve_addr);

    qemu_put_betls(f, &env->msr);

    for (i = 0; i < 4; i++)

        qemu_put_betls(f, &env->tgpr[i]);

    for (i = 0; i < 32; i++) {

        union {

            float64 d;

            uint64_t l;

        } u;

        u.d = env->fpr[i];

        qemu_put_be64(f, u.l);

    }

    qemu_put_be32s(f, &env->fpscr);

    qemu_put_sbe32s(f, &env->access_type);

#if !defined(CONFIG_USER_ONLY)

#if defined(TARGET_PPC64)

    qemu_put_betls(f, &env->asr);

    qemu_put_sbe32s(f, &env->slb_nr);

#endif

    qemu_put_betls(f, &env->sdr1);

    for (i = 0; i < 32; i++)

        qemu_put_betls(f, &env->sr[i]);

    for (i = 0; i < 2; i++)

        for (j = 0; j < 8; j++)

            qemu_put_betls(f, &env->DBAT[i][j]);

    for (i = 0; i < 2; i++)

        for (j = 0; j < 8; j++)

            qemu_put_betls(f, &env->IBAT[i][j]);

    qemu_put_sbe32s(f, &env->nb_tlb);

    qemu_put_sbe32s(f, &env->tlb_per_way);

    qemu_put_sbe32s(f, &env->nb_ways);

    qemu_put_sbe32s(f, &env->last_way);

    qemu_put_sbe32s(f, &env->id_tlbs);

    qemu_put_sbe32s(f, &env->nb_pids);

    if (env->tlb) {

        

        for (i = 0; i < env->nb_tlb; i++) {

            qemu_put_betls(f, &env->tlb[i].tlb6.pte0);

            qemu_put_betls(f, &env->tlb[i].tlb6.pte1);

            qemu_put_betls(f, &env->tlb[i].tlb6.EPN);

        }

    }

    for (i = 0; i < 4; i++)

        qemu_put_betls(f, &env->pb[i]);

#endif

    for (i = 0; i < 1024; i++)

        qemu_put_betls(f, &env->spr[i]);

    qemu_put_be32s(f, &env->vscr);

    qemu_put_be64s(f, &env->spe_acc);

    qemu_put_be32s(f, &env->spe_fscr);

    qemu_put_betls(f, &env->msr_mask);

    qemu_put_be32s(f, &env->flags);

    qemu_put_sbe32s(f, &env->error_code);

    qemu_put_be32s(f, &env->pending_interrupts);

#if !defined(CONFIG_USER_ONLY)

    qemu_put_be32s(f, &env->irq_input_state);

    for (i = 0; i < POWERPC_EXCP_NB; i++)

        qemu_put_betls(f, &env->excp_vectors[i]);

    qemu_put_betls(f, &env->excp_prefix);

    qemu_put_betls(f, &env->hreset_excp_prefix);

    qemu_put_betls(f, &env->ivor_mask);

    qemu_put_betls(f, &env->ivpr_mask);

    qemu_put_betls(f, &env->hreset_vector);

#endif

    qemu_put_betls(f, &env->nip);

    qemu_put_betls(f, &env->hflags);

    qemu_put_betls(f, &env->hflags_nmsr);

    qemu_put_sbe32s(f, &env->mmu_idx);

    qemu_put_sbe32s(f, &env->power_mode);

}

    cpu_synchronize_state(env);     cpu_synchronize_state(env);     cpu_synchronize_state(env);     cpu_synchronize_state(env);     cpu_synchronize_state(env);     cpu_synchronize_state(env);     cpu_synchronize_state(env);     cpu_synchronize_state(env);
void FUNC_0(QEMUFile *VAR_0, void *VAR_1)

{

    CPUState *env = (CPUState *)VAR_1;

    unsigned int VAR_2, VAR_3;



    cpu_synchronize_state(env);



    for (VAR_2 = 0; VAR_2 < 32; VAR_2++)

        qemu_put_betls(VAR_0, &env->gpr[VAR_2]);

#if !defined(TARGET_PPC64)

    for (VAR_2 = 0; VAR_2 < 32; VAR_2++)

        qemu_put_betls(VAR_0, &env->gprh[VAR_2]);

#endif

    qemu_put_betls(VAR_0, &env->lr);

    qemu_put_betls(VAR_0, &env->ctr);

    for (VAR_2 = 0; VAR_2 < 8; VAR_2++)

        qemu_put_be32s(VAR_0, &env->crf[VAR_2]);

    qemu_put_betls(VAR_0, &env->xer);

    qemu_put_betls(VAR_0, &env->reserve_addr);

    qemu_put_betls(VAR_0, &env->msr);

    for (VAR_2 = 0; VAR_2 < 4; VAR_2++)

        qemu_put_betls(VAR_0, &env->tgpr[VAR_2]);

    for (VAR_2 = 0; VAR_2 < 32; VAR_2++) {

        union {

            float64 d;

            uint64_t l;

        } VAR_4;

        VAR_4.d = env->fpr[VAR_2];

        qemu_put_be64(VAR_0, VAR_4.l);

    }

    qemu_put_be32s(VAR_0, &env->fpscr);

    qemu_put_sbe32s(VAR_0, &env->access_type);

#if !defined(CONFIG_USER_ONLY)

#if defined(TARGET_PPC64)

    qemu_put_betls(VAR_0, &env->asr);

    qemu_put_sbe32s(VAR_0, &env->slb_nr);

#endif

    qemu_put_betls(VAR_0, &env->sdr1);

    for (VAR_2 = 0; VAR_2 < 32; VAR_2++)

        qemu_put_betls(VAR_0, &env->sr[VAR_2]);

    for (VAR_2 = 0; VAR_2 < 2; VAR_2++)

        for (VAR_3 = 0; VAR_3 < 8; VAR_3++)

            qemu_put_betls(VAR_0, &env->DBAT[VAR_2][VAR_3]);

    for (VAR_2 = 0; VAR_2 < 2; VAR_2++)

        for (VAR_3 = 0; VAR_3 < 8; VAR_3++)

            qemu_put_betls(VAR_0, &env->IBAT[VAR_2][VAR_3]);

    qemu_put_sbe32s(VAR_0, &env->nb_tlb);

    qemu_put_sbe32s(VAR_0, &env->tlb_per_way);

    qemu_put_sbe32s(VAR_0, &env->nb_ways);

    qemu_put_sbe32s(VAR_0, &env->last_way);

    qemu_put_sbe32s(VAR_0, &env->id_tlbs);

    qemu_put_sbe32s(VAR_0, &env->nb_pids);

    if (env->tlb) {

        

        for (VAR_2 = 0; VAR_2 < env->nb_tlb; VAR_2++) {

            qemu_put_betls(VAR_0, &env->tlb[VAR_2].tlb6.pte0);

            qemu_put_betls(VAR_0, &env->tlb[VAR_2].tlb6.pte1);

            qemu_put_betls(VAR_0, &env->tlb[VAR_2].tlb6.EPN);

        }

    }

    for (VAR_2 = 0; VAR_2 < 4; VAR_2++)

        qemu_put_betls(VAR_0, &env->pb[VAR_2]);

#endif

    for (VAR_2 = 0; VAR_2 < 1024; VAR_2++)

        qemu_put_betls(VAR_0, &env->spr[VAR_2]);

    qemu_put_be32s(VAR_0, &env->vscr);

    qemu_put_be64s(VAR_0, &env->spe_acc);

    qemu_put_be32s(VAR_0, &env->spe_fscr);

    qemu_put_betls(VAR_0, &env->msr_mask);

    qemu_put_be32s(VAR_0, &env->flags);

    qemu_put_sbe32s(VAR_0, &env->error_code);

    qemu_put_be32s(VAR_0, &env->pending_interrupts);

#if !defined(CONFIG_USER_ONLY)

    qemu_put_be32s(VAR_0, &env->irq_input_state);

    for (VAR_2 = 0; VAR_2 < POWERPC_EXCP_NB; VAR_2++)

        qemu_put_betls(VAR_0, &env->excp_vectors[VAR_2]);

    qemu_put_betls(VAR_0, &env->excp_prefix);

    qemu_put_betls(VAR_0, &env->hreset_excp_prefix);

    qemu_put_betls(VAR_0, &env->ivor_mask);

    qemu_put_betls(VAR_0, &env->ivpr_mask);

    qemu_put_betls(VAR_0, &env->hreset_vector);

#endif

    qemu_put_betls(VAR_0, &env->nip);

    qemu_put_betls(VAR_0, &env->hflags);

    qemu_put_betls(VAR_0, &env->hflags_nmsr);

    qemu_put_sbe32s(VAR_0, &env->mmu_idx);

    qemu_put_sbe32s(VAR_0, &env->power_mode);

}

void FUNC_0(QEMUFile *VAR_0, void *VAR_1)
{ CPUState *env = (CPUState *)VAR_1; unsigned int VAR_2, VAR_3; cpu_synchronize_state(env); for (VAR_2 = 0; VAR_2 < 32; VAR_2++) qemu_put_betls(VAR_0, &env->gpr[VAR_2]); #if !defined(TARGET_PPC64)
for (VAR_2 = 0; VAR_2 < 32; VAR_2++) qemu_put_betls(VAR_0, &env->gprh[VAR_2]); #endif
qemu_put_betls(VAR_0, &env->lr); qemu_put_betls(VAR_0, &env->ctr); for (VAR_2 = 0; VAR_2 < 8; VAR_2++) qemu_put_be32s(VAR_0, &env->crf[VAR_2]); qemu_put_betls(VAR_0, &env->xer); qemu_put_betls(VAR_0, &env->reserve_addr); qemu_put_betls(VAR_0, &env->msr); for (VAR_2 = 0; VAR_2 < 4; VAR_2++) qemu_put_betls(VAR_0, &env->tgpr[VAR_2]); for (VAR_2 = 0; VAR_2 < 32; VAR_2++) { union { float64 d; uint64_t l; } VAR_4; VAR_4.d = env->fpr[VAR_2]; qemu_put_be64(VAR_0, VAR_4.l); } qemu_put_be32s(VAR_0, &env->fpscr); qemu_put_sbe32s(VAR_0, &env->access_type); #if !defined(CONFIG_USER_ONLY)
#if defined(TARGET_PPC64)
qemu_put_betls(VAR_0, &env->asr); qemu_put_sbe32s(VAR_0, &env->slb_nr); #endif
qemu_put_betls(VAR_0, &env->sdr1); for (VAR_2 = 0; VAR_2 < 32; VAR_2++) qemu_put_betls(VAR_0, &env->sr[VAR_2]); for (VAR_2 = 0; VAR_2 < 2; VAR_2++) for (VAR_3 = 0; VAR_3 < 8; VAR_3++) qemu_put_betls(VAR_0, &env->DBAT[VAR_2][VAR_3]); for (VAR_2 = 0; VAR_2 < 2; VAR_2++) for (VAR_3 = 0; VAR_3 < 8; VAR_3++) qemu_put_betls(VAR_0, &env->IBAT[VAR_2][VAR_3]); qemu_put_sbe32s(VAR_0, &env->nb_tlb); qemu_put_sbe32s(VAR_0, &env->tlb_per_way); qemu_put_sbe32s(VAR_0, &env->nb_ways); qemu_put_sbe32s(VAR_0, &env->last_way); qemu_put_sbe32s(VAR_0, &env->id_tlbs); qemu_put_sbe32s(VAR_0, &env->nb_pids); if (env->tlb) { for (VAR_2 = 0; VAR_2 < env->nb_tlb; VAR_2++) { qemu_put_betls(VAR_0, &env->tlb[VAR_2].tlb6.pte0); qemu_put_betls(VAR_0, &env->tlb[VAR_2].tlb6.pte1); qemu_put_betls(VAR_0, &env->tlb[VAR_2].tlb6.EPN); } } for (VAR_2 = 0; VAR_2 < 4; VAR_2++) qemu_put_betls(VAR_0, &env->pb[VAR_2]); #endif
for (VAR_2 = 0; VAR_2 < 1024; VAR_2++) qemu_put_betls(VAR_0, &env->spr[VAR_2]); qemu_put_be32s(VAR_0, &env->vscr); qemu_put_be64s(VAR_0, &env->spe_acc); qemu_put_be32s(VAR_0, &env->spe_fscr); qemu_put_betls(VAR_0, &env->msr_mask); qemu_put_be32s(VAR_0, &env->flags); qemu_put_sbe32s(VAR_0, &env->error_code); qemu_put_be32s(VAR_0, &env->pending_interrupts); #if !defined(CONFIG_USER_ONLY)
qemu_put_be32s(VAR_0, &env->irq_input_state); for (VAR_2 = 0; VAR_2 < POWERPC_EXCP_NB; VAR_2++) qemu_put_betls(VAR_0, &env->excp_vectors[VAR_2]); qemu_put_betls(VAR_0, &env->excp_prefix); qemu_put_betls(VAR_0, &env->hreset_excp_prefix); qemu_put_betls(VAR_0, &env->ivor_mask); qemu_put_betls(VAR_0, &env->ivpr_mask); qemu_put_betls(VAR_0, &env->hreset_vector); #endif
qemu_put_betls(VAR_0, &env->nip); qemu_put_betls(VAR_0, &env->hflags); qemu_put_betls(VAR_0, &env->hflags_nmsr); qemu_put_sbe32s(VAR_0, &env->mmu_idx); qemu_put_sbe32s(VAR_0, &env->power_mode); }