int kvm_arch_get_registers(CPUState *env)

{

    struct kvm_regs regs;

    struct kvm_sregs sregs;

    uint32_t cr;

    int i, ret;



    ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, &regs);

    if (ret < 0)

        return ret;



    cr = regs.cr;

    for (i = 7; i >= 0; i--) {

        env->crf[i] = cr & 15;

        cr >>= 4;

    }



    env->ctr = regs.ctr;

    env->lr = regs.lr;

    env->xer = regs.xer;

    env->msr = regs.msr;

    env->nip = regs.pc;



    env->spr[SPR_SRR0] = regs.srr0;

    env->spr[SPR_SRR1] = regs.srr1;



    env->spr[SPR_SPRG0] = regs.sprg0;

    env->spr[SPR_SPRG1] = regs.sprg1;

    env->spr[SPR_SPRG2] = regs.sprg2;

    env->spr[SPR_SPRG3] = regs.sprg3;

    env->spr[SPR_SPRG4] = regs.sprg4;

    env->spr[SPR_SPRG5] = regs.sprg5;

    env->spr[SPR_SPRG6] = regs.sprg6;

    env->spr[SPR_SPRG7] = regs.sprg7;



    env->spr[SPR_BOOKE_PID] = regs.pid;



    for (i = 0;i < 32; i++)

        env->gpr[i] = regs.gpr[i];



#ifdef KVM_CAP_PPC_BOOKE_SREGS

    if (cap_booke_sregs) {

        ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs);

        if (ret < 0) {

            return ret;

        }



        if (sregs.u.e.features & KVM_SREGS_E_BASE) {

            env->spr[SPR_BOOKE_CSRR0] = sregs.u.e.csrr0;

            env->spr[SPR_BOOKE_CSRR1] = sregs.u.e.csrr1;

            env->spr[SPR_BOOKE_ESR] = sregs.u.e.esr;

            env->spr[SPR_BOOKE_DEAR] = sregs.u.e.dear;

            env->spr[SPR_BOOKE_MCSR] = sregs.u.e.mcsr;

            env->spr[SPR_BOOKE_TSR] = sregs.u.e.tsr;

            env->spr[SPR_BOOKE_TCR] = sregs.u.e.tcr;

            env->spr[SPR_DECR] = sregs.u.e.dec;

            env->spr[SPR_TBL] = sregs.u.e.tb & 0xffffffff;

            env->spr[SPR_TBU] = sregs.u.e.tb >> 32;

            env->spr[SPR_VRSAVE] = sregs.u.e.vrsave;

        }



        if (sregs.u.e.features & KVM_SREGS_E_ARCH206) {

            env->spr[SPR_BOOKE_PIR] = sregs.u.e.pir;

            env->spr[SPR_BOOKE_MCSRR0] = sregs.u.e.mcsrr0;

            env->spr[SPR_BOOKE_MCSRR1] = sregs.u.e.mcsrr1;

            env->spr[SPR_BOOKE_DECAR] = sregs.u.e.decar;

            env->spr[SPR_BOOKE_IVPR] = sregs.u.e.ivpr;

        }



        if (sregs.u.e.features & KVM_SREGS_E_64) {

            env->spr[SPR_BOOKE_EPCR] = sregs.u.e.epcr;

        }



        if (sregs.u.e.features & KVM_SREGS_E_SPRG8) {

            env->spr[SPR_BOOKE_SPRG8] = sregs.u.e.sprg8;

        }



        if (sregs.u.e.features & KVM_SREGS_E_IVOR) {

            env->spr[SPR_BOOKE_IVOR0] = sregs.u.e.ivor_low[0];

            env->spr[SPR_BOOKE_IVOR1] = sregs.u.e.ivor_low[1];

            env->spr[SPR_BOOKE_IVOR2] = sregs.u.e.ivor_low[2];

            env->spr[SPR_BOOKE_IVOR3] = sregs.u.e.ivor_low[3];

            env->spr[SPR_BOOKE_IVOR4] = sregs.u.e.ivor_low[4];

            env->spr[SPR_BOOKE_IVOR5] = sregs.u.e.ivor_low[5];

            env->spr[SPR_BOOKE_IVOR6] = sregs.u.e.ivor_low[6];

            env->spr[SPR_BOOKE_IVOR7] = sregs.u.e.ivor_low[7];

            env->spr[SPR_BOOKE_IVOR8] = sregs.u.e.ivor_low[8];

            env->spr[SPR_BOOKE_IVOR9] = sregs.u.e.ivor_low[9];

            env->spr[SPR_BOOKE_IVOR10] = sregs.u.e.ivor_low[10];

            env->spr[SPR_BOOKE_IVOR11] = sregs.u.e.ivor_low[11];

            env->spr[SPR_BOOKE_IVOR12] = sregs.u.e.ivor_low[12];

            env->spr[SPR_BOOKE_IVOR13] = sregs.u.e.ivor_low[13];

            env->spr[SPR_BOOKE_IVOR14] = sregs.u.e.ivor_low[14];

            env->spr[SPR_BOOKE_IVOR15] = sregs.u.e.ivor_low[15];



            if (sregs.u.e.features & KVM_SREGS_E_SPE) {

                env->spr[SPR_BOOKE_IVOR32] = sregs.u.e.ivor_high[0];

                env->spr[SPR_BOOKE_IVOR33] = sregs.u.e.ivor_high[1];

                env->spr[SPR_BOOKE_IVOR34] = sregs.u.e.ivor_high[2];

            }



            if (sregs.u.e.features & KVM_SREGS_E_PM) {

                env->spr[SPR_BOOKE_IVOR35] = sregs.u.e.ivor_high[3];

            }



            if (sregs.u.e.features & KVM_SREGS_E_PC) {

                env->spr[SPR_BOOKE_IVOR36] = sregs.u.e.ivor_high[4];

                env->spr[SPR_BOOKE_IVOR37] = sregs.u.e.ivor_high[5];

            }

        }



        if (sregs.u.e.features & KVM_SREGS_E_ARCH206_MMU) {

            env->spr[SPR_BOOKE_MAS0] = sregs.u.e.mas0;

            env->spr[SPR_BOOKE_MAS1] = sregs.u.e.mas1;

            env->spr[SPR_BOOKE_MAS2] = sregs.u.e.mas2;

            env->spr[SPR_BOOKE_MAS3] = sregs.u.e.mas7_3 & 0xffffffff;

            env->spr[SPR_BOOKE_MAS4] = sregs.u.e.mas4;

            env->spr[SPR_BOOKE_MAS6] = sregs.u.e.mas6;

            env->spr[SPR_BOOKE_MAS7] = sregs.u.e.mas7_3 >> 32;

            env->spr[SPR_MMUCFG] = sregs.u.e.mmucfg;

            env->spr[SPR_BOOKE_TLB0CFG] = sregs.u.e.tlbcfg[0];

            env->spr[SPR_BOOKE_TLB1CFG] = sregs.u.e.tlbcfg[1];

        }



        if (sregs.u.e.features & KVM_SREGS_EXP) {

            env->spr[SPR_BOOKE_EPR] = sregs.u.e.epr;

        }



        if (sregs.u.e.features & KVM_SREGS_E_PD) {

            env->spr[SPR_BOOKE_EPLC] = sregs.u.e.eplc;

            env->spr[SPR_BOOKE_EPSC] = sregs.u.e.epsc;

        }



        if (sregs.u.e.impl_id == KVM_SREGS_E_IMPL_FSL) {

            env->spr[SPR_E500_SVR] = sregs.u.e.impl.fsl.svr;

            env->spr[SPR_Exxx_MCAR] = sregs.u.e.impl.fsl.mcar;

            env->spr[SPR_HID0] = sregs.u.e.impl.fsl.hid0;



            if (sregs.u.e.impl.fsl.features & KVM_SREGS_E_FSL_PIDn) {

                env->spr[SPR_BOOKE_PID1] = sregs.u.e.impl.fsl.pid1;

                env->spr[SPR_BOOKE_PID2] = sregs.u.e.impl.fsl.pid2;

            }

        }

    }

#endif



#ifdef KVM_CAP_PPC_SEGSTATE

    if (cap_segstate) {

        ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs);

        if (ret < 0) {

            return ret;

        }



        ppc_store_sdr1(env, sregs.u.s.sdr1);



        /* Sync SLB */

#ifdef TARGET_PPC64

        for (i = 0; i < 64; i++) {

            ppc_store_slb(env, sregs.u.s.ppc64.slb[i].slbe,

                               sregs.u.s.ppc64.slb[i].slbv);

        }

#endif



        /* Sync SRs */

        for (i = 0; i < 16; i++) {

            env->sr[i] = sregs.u.s.ppc32.sr[i];

        }



        /* Sync BATs */

        for (i = 0; i < 8; i++) {

            env->DBAT[0][i] = sregs.u.s.ppc32.dbat[i] & 0xffffffff;

            env->DBAT[1][i] = sregs.u.s.ppc32.dbat[i] >> 32;

            env->IBAT[0][i] = sregs.u.s.ppc32.ibat[i] & 0xffffffff;

            env->IBAT[1][i] = sregs.u.s.ppc32.ibat[i] >> 32;

        }

    }

#endif



    return 0;

}

int kvm_arch_get_registers(CPUState *env)

{

    struct kvm_regs regs;

    struct kvm_sregs sregs;

    uint32_t cr;

    int i, ret;



    ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, &regs);

    if (ret < 0)

        return ret;



    cr = regs.cr;

    for (i = 7; i >= 0; i--) {

        env->crf[i] = cr & 15;

        cr >>= 4;

    }



    env->ctr = regs.ctr;

    env->lr = regs.lr;

    env->xer = regs.xer;

    env->msr = regs.msr;

    env->nip = regs.pc;



    env->spr[SPR_SRR0] = regs.srr0;

    env->spr[SPR_SRR1] = regs.srr1;



    env->spr[SPR_SPRG0] = regs.sprg0;

    env->spr[SPR_SPRG1] = regs.sprg1;

    env->spr[SPR_SPRG2] = regs.sprg2;

    env->spr[SPR_SPRG3] = regs.sprg3;

    env->spr[SPR_SPRG4] = regs.sprg4;

    env->spr[SPR_SPRG5] = regs.sprg5;

    env->spr[SPR_SPRG6] = regs.sprg6;

    env->spr[SPR_SPRG7] = regs.sprg7;



    env->spr[SPR_BOOKE_PID] = regs.pid;



    for (i = 0;i < 32; i++)

        env->gpr[i] = regs.gpr[i];



#ifdef KVM_CAP_PPC_BOOKE_SREGS

    if (cap_booke_sregs) {

        ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs);

        if (ret < 0) {

            return ret;

        }



        if (sregs.u.e.features & KVM_SREGS_E_BASE) {

            env->spr[SPR_BOOKE_CSRR0] = sregs.u.e.csrr0;

            env->spr[SPR_BOOKE_CSRR1] = sregs.u.e.csrr1;

            env->spr[SPR_BOOKE_ESR] = sregs.u.e.esr;

            env->spr[SPR_BOOKE_DEAR] = sregs.u.e.dear;

            env->spr[SPR_BOOKE_MCSR] = sregs.u.e.mcsr;

            env->spr[SPR_BOOKE_TSR] = sregs.u.e.tsr;

            env->spr[SPR_BOOKE_TCR] = sregs.u.e.tcr;

            env->spr[SPR_DECR] = sregs.u.e.dec;

            env->spr[SPR_TBL] = sregs.u.e.tb & 0xffffffff;

            env->spr[SPR_TBU] = sregs.u.e.tb >> 32;

            env->spr[SPR_VRSAVE] = sregs.u.e.vrsave;

        }



        if (sregs.u.e.features & KVM_SREGS_E_ARCH206) {

            env->spr[SPR_BOOKE_PIR] = sregs.u.e.pir;

            env->spr[SPR_BOOKE_MCSRR0] = sregs.u.e.mcsrr0;

            env->spr[SPR_BOOKE_MCSRR1] = sregs.u.e.mcsrr1;

            env->spr[SPR_BOOKE_DECAR] = sregs.u.e.decar;

            env->spr[SPR_BOOKE_IVPR] = sregs.u.e.ivpr;

        }



        if (sregs.u.e.features & KVM_SREGS_E_64) {

            env->spr[SPR_BOOKE_EPCR] = sregs.u.e.epcr;

        }



        if (sregs.u.e.features & KVM_SREGS_E_SPRG8) {

            env->spr[SPR_BOOKE_SPRG8] = sregs.u.e.sprg8;

        }



        if (sregs.u.e.features & KVM_SREGS_E_IVOR) {

            env->spr[SPR_BOOKE_IVOR0] = sregs.u.e.ivor_low[0];

            env->spr[SPR_BOOKE_IVOR1] = sregs.u.e.ivor_low[1];

            env->spr[SPR_BOOKE_IVOR2] = sregs.u.e.ivor_low[2];

            env->spr[SPR_BOOKE_IVOR3] = sregs.u.e.ivor_low[3];

            env->spr[SPR_BOOKE_IVOR4] = sregs.u.e.ivor_low[4];

            env->spr[SPR_BOOKE_IVOR5] = sregs.u.e.ivor_low[5];

            env->spr[SPR_BOOKE_IVOR6] = sregs.u.e.ivor_low[6];

            env->spr[SPR_BOOKE_IVOR7] = sregs.u.e.ivor_low[7];

            env->spr[SPR_BOOKE_IVOR8] = sregs.u.e.ivor_low[8];

            env->spr[SPR_BOOKE_IVOR9] = sregs.u.e.ivor_low[9];

            env->spr[SPR_BOOKE_IVOR10] = sregs.u.e.ivor_low[10];

            env->spr[SPR_BOOKE_IVOR11] = sregs.u.e.ivor_low[11];

            env->spr[SPR_BOOKE_IVOR12] = sregs.u.e.ivor_low[12];

            env->spr[SPR_BOOKE_IVOR13] = sregs.u.e.ivor_low[13];

            env->spr[SPR_BOOKE_IVOR14] = sregs.u.e.ivor_low[14];

            env->spr[SPR_BOOKE_IVOR15] = sregs.u.e.ivor_low[15];



            if (sregs.u.e.features & KVM_SREGS_E_SPE) {

                env->spr[SPR_BOOKE_IVOR32] = sregs.u.e.ivor_high[0];

                env->spr[SPR_BOOKE_IVOR33] = sregs.u.e.ivor_high[1];

                env->spr[SPR_BOOKE_IVOR34] = sregs.u.e.ivor_high[2];

            }



            if (sregs.u.e.features & KVM_SREGS_E_PM) {

                env->spr[SPR_BOOKE_IVOR35] = sregs.u.e.ivor_high[3];

            }



            if (sregs.u.e.features & KVM_SREGS_E_PC) {

                env->spr[SPR_BOOKE_IVOR36] = sregs.u.e.ivor_high[4];

                env->spr[SPR_BOOKE_IVOR37] = sregs.u.e.ivor_high[5];

            }

        }



        if (sregs.u.e.features & KVM_SREGS_E_ARCH206_MMU) {

            env->spr[SPR_BOOKE_MAS0] = sregs.u.e.mas0;

            env->spr[SPR_BOOKE_MAS1] = sregs.u.e.mas1;

            env->spr[SPR_BOOKE_MAS2] = sregs.u.e.mas2;

            env->spr[SPR_BOOKE_MAS3] = sregs.u.e.mas7_3 & 0xffffffff;

            env->spr[SPR_BOOKE_MAS4] = sregs.u.e.mas4;

            env->spr[SPR_BOOKE_MAS6] = sregs.u.e.mas6;

            env->spr[SPR_BOOKE_MAS7] = sregs.u.e.mas7_3 >> 32;

            env->spr[SPR_MMUCFG] = sregs.u.e.mmucfg;

            env->spr[SPR_BOOKE_TLB0CFG] = sregs.u.e.tlbcfg[0];

            env->spr[SPR_BOOKE_TLB1CFG] = sregs.u.e.tlbcfg[1];

        }



        if (sregs.u.e.features & KVM_SREGS_EXP) {

            env->spr[SPR_BOOKE_EPR] = sregs.u.e.epr;

        }



        if (sregs.u.e.features & KVM_SREGS_E_PD) {

            env->spr[SPR_BOOKE_EPLC] = sregs.u.e.eplc;

            env->spr[SPR_BOOKE_EPSC] = sregs.u.e.epsc;

        }



        if (sregs.u.e.impl_id == KVM_SREGS_E_IMPL_FSL) {

            env->spr[SPR_E500_SVR] = sregs.u.e.impl.fsl.svr;

            env->spr[SPR_Exxx_MCAR] = sregs.u.e.impl.fsl.mcar;

            env->spr[SPR_HID0] = sregs.u.e.impl.fsl.hid0;



            if (sregs.u.e.impl.fsl.features & KVM_SREGS_E_FSL_PIDn) {

                env->spr[SPR_BOOKE_PID1] = sregs.u.e.impl.fsl.pid1;

                env->spr[SPR_BOOKE_PID2] = sregs.u.e.impl.fsl.pid2;

            }

        }

    }

#endif



#ifdef KVM_CAP_PPC_SEGSTATE

    if (cap_segstate) {

        ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs);

        if (ret < 0) {

            return ret;

        }



        ppc_store_sdr1(env, sregs.u.s.sdr1);



        

#ifdef TARGET_PPC64

        for (i = 0; i < 64; i++) {

            ppc_store_slb(env, sregs.u.s.ppc64.slb[i].slbe,

                               sregs.u.s.ppc64.slb[i].slbv);

        }

#endif



        

        for (i = 0; i < 16; i++) {

            env->sr[i] = sregs.u.s.ppc32.sr[i];

        }



        

        for (i = 0; i < 8; i++) {

            env->DBAT[0][i] = sregs.u.s.ppc32.dbat[i] & 0xffffffff;

            env->DBAT[1][i] = sregs.u.s.ppc32.dbat[i] >> 32;

            env->IBAT[0][i] = sregs.u.s.ppc32.ibat[i] & 0xffffffff;

            env->IBAT[1][i] = sregs.u.s.ppc32.ibat[i] >> 32;

        }

    }

#endif



    return 0;

}

#ifdef KVM_CAP_PPC_BOOKE_SREGS #endif #ifdef KVM_CAP_PPC_BOOKE_SREGS #ifdef KVM_CAP_PPC_SEGSTATE
int FUNC_0(CPUState *VAR_0)

{

    struct kvm_regs VAR_1;

    struct kvm_sregs VAR_2;

    uint32_t cr;

    int VAR_3, VAR_4;



    VAR_4 = kvm_vcpu_ioctl(VAR_0, KVM_GET_REGS, &VAR_1);

    if (VAR_4 < 0)

        return VAR_4;



    cr = VAR_1.cr;

    for (VAR_3 = 7; VAR_3 >= 0; VAR_3--) {

        VAR_0->crf[VAR_3] = cr & 15;

        cr >>= 4;

    }



    VAR_0->ctr = VAR_1.ctr;

    VAR_0->lr = VAR_1.lr;

    VAR_0->xer = VAR_1.xer;

    VAR_0->msr = VAR_1.msr;

    VAR_0->nip = VAR_1.pc;



    VAR_0->spr[SPR_SRR0] = VAR_1.srr0;

    VAR_0->spr[SPR_SRR1] = VAR_1.srr1;



    VAR_0->spr[SPR_SPRG0] = VAR_1.sprg0;

    VAR_0->spr[SPR_SPRG1] = VAR_1.sprg1;

    VAR_0->spr[SPR_SPRG2] = VAR_1.sprg2;

    VAR_0->spr[SPR_SPRG3] = VAR_1.sprg3;

    VAR_0->spr[SPR_SPRG4] = VAR_1.sprg4;

    VAR_0->spr[SPR_SPRG5] = VAR_1.sprg5;

    VAR_0->spr[SPR_SPRG6] = VAR_1.sprg6;

    VAR_0->spr[SPR_SPRG7] = VAR_1.sprg7;



    VAR_0->spr[SPR_BOOKE_PID] = VAR_1.pid;



    for (VAR_3 = 0;VAR_3 < 32; VAR_3++)

        VAR_0->gpr[VAR_3] = VAR_1.gpr[VAR_3];



#ifdef KVM_CAP_PPC_BOOKE_SREGS

    if (cap_booke_sregs) {

        VAR_4 = kvm_vcpu_ioctl(VAR_0, KVM_GET_SREGS, &VAR_2);

        if (VAR_4 < 0) {

            return VAR_4;

        }



        if (VAR_2.u.e.features & KVM_SREGS_E_BASE) {

            VAR_0->spr[SPR_BOOKE_CSRR0] = VAR_2.u.e.csrr0;

            VAR_0->spr[SPR_BOOKE_CSRR1] = VAR_2.u.e.csrr1;

            VAR_0->spr[SPR_BOOKE_ESR] = VAR_2.u.e.esr;

            VAR_0->spr[SPR_BOOKE_DEAR] = VAR_2.u.e.dear;

            VAR_0->spr[SPR_BOOKE_MCSR] = VAR_2.u.e.mcsr;

            VAR_0->spr[SPR_BOOKE_TSR] = VAR_2.u.e.tsr;

            VAR_0->spr[SPR_BOOKE_TCR] = VAR_2.u.e.tcr;

            VAR_0->spr[SPR_DECR] = VAR_2.u.e.dec;

            VAR_0->spr[SPR_TBL] = VAR_2.u.e.tb & 0xffffffff;

            VAR_0->spr[SPR_TBU] = VAR_2.u.e.tb >> 32;

            VAR_0->spr[SPR_VRSAVE] = VAR_2.u.e.vrsave;

        }



        if (VAR_2.u.e.features & KVM_SREGS_E_ARCH206) {

            VAR_0->spr[SPR_BOOKE_PIR] = VAR_2.u.e.pir;

            VAR_0->spr[SPR_BOOKE_MCSRR0] = VAR_2.u.e.mcsrr0;

            VAR_0->spr[SPR_BOOKE_MCSRR1] = VAR_2.u.e.mcsrr1;

            VAR_0->spr[SPR_BOOKE_DECAR] = VAR_2.u.e.decar;

            VAR_0->spr[SPR_BOOKE_IVPR] = VAR_2.u.e.ivpr;

        }



        if (VAR_2.u.e.features & KVM_SREGS_E_64) {

            VAR_0->spr[SPR_BOOKE_EPCR] = VAR_2.u.e.epcr;

        }



        if (VAR_2.u.e.features & KVM_SREGS_E_SPRG8) {

            VAR_0->spr[SPR_BOOKE_SPRG8] = VAR_2.u.e.sprg8;

        }



        if (VAR_2.u.e.features & KVM_SREGS_E_IVOR) {

            VAR_0->spr[SPR_BOOKE_IVOR0] = VAR_2.u.e.ivor_low[0];

            VAR_0->spr[SPR_BOOKE_IVOR1] = VAR_2.u.e.ivor_low[1];

            VAR_0->spr[SPR_BOOKE_IVOR2] = VAR_2.u.e.ivor_low[2];

            VAR_0->spr[SPR_BOOKE_IVOR3] = VAR_2.u.e.ivor_low[3];

            VAR_0->spr[SPR_BOOKE_IVOR4] = VAR_2.u.e.ivor_low[4];

            VAR_0->spr[SPR_BOOKE_IVOR5] = VAR_2.u.e.ivor_low[5];

            VAR_0->spr[SPR_BOOKE_IVOR6] = VAR_2.u.e.ivor_low[6];

            VAR_0->spr[SPR_BOOKE_IVOR7] = VAR_2.u.e.ivor_low[7];

            VAR_0->spr[SPR_BOOKE_IVOR8] = VAR_2.u.e.ivor_low[8];

            VAR_0->spr[SPR_BOOKE_IVOR9] = VAR_2.u.e.ivor_low[9];

            VAR_0->spr[SPR_BOOKE_IVOR10] = VAR_2.u.e.ivor_low[10];

            VAR_0->spr[SPR_BOOKE_IVOR11] = VAR_2.u.e.ivor_low[11];

            VAR_0->spr[SPR_BOOKE_IVOR12] = VAR_2.u.e.ivor_low[12];

            VAR_0->spr[SPR_BOOKE_IVOR13] = VAR_2.u.e.ivor_low[13];

            VAR_0->spr[SPR_BOOKE_IVOR14] = VAR_2.u.e.ivor_low[14];

            VAR_0->spr[SPR_BOOKE_IVOR15] = VAR_2.u.e.ivor_low[15];



            if (VAR_2.u.e.features & KVM_SREGS_E_SPE) {

                VAR_0->spr[SPR_BOOKE_IVOR32] = VAR_2.u.e.ivor_high[0];

                VAR_0->spr[SPR_BOOKE_IVOR33] = VAR_2.u.e.ivor_high[1];

                VAR_0->spr[SPR_BOOKE_IVOR34] = VAR_2.u.e.ivor_high[2];

            }



            if (VAR_2.u.e.features & KVM_SREGS_E_PM) {

                VAR_0->spr[SPR_BOOKE_IVOR35] = VAR_2.u.e.ivor_high[3];

            }



            if (VAR_2.u.e.features & KVM_SREGS_E_PC) {

                VAR_0->spr[SPR_BOOKE_IVOR36] = VAR_2.u.e.ivor_high[4];

                VAR_0->spr[SPR_BOOKE_IVOR37] = VAR_2.u.e.ivor_high[5];

            }

        }



        if (VAR_2.u.e.features & KVM_SREGS_E_ARCH206_MMU) {

            VAR_0->spr[SPR_BOOKE_MAS0] = VAR_2.u.e.mas0;

            VAR_0->spr[SPR_BOOKE_MAS1] = VAR_2.u.e.mas1;

            VAR_0->spr[SPR_BOOKE_MAS2] = VAR_2.u.e.mas2;

            VAR_0->spr[SPR_BOOKE_MAS3] = VAR_2.u.e.mas7_3 & 0xffffffff;

            VAR_0->spr[SPR_BOOKE_MAS4] = VAR_2.u.e.mas4;

            VAR_0->spr[SPR_BOOKE_MAS6] = VAR_2.u.e.mas6;

            VAR_0->spr[SPR_BOOKE_MAS7] = VAR_2.u.e.mas7_3 >> 32;

            VAR_0->spr[SPR_MMUCFG] = VAR_2.u.e.mmucfg;

            VAR_0->spr[SPR_BOOKE_TLB0CFG] = VAR_2.u.e.tlbcfg[0];

            VAR_0->spr[SPR_BOOKE_TLB1CFG] = VAR_2.u.e.tlbcfg[1];

        }



        if (VAR_2.u.e.features & KVM_SREGS_EXP) {

            VAR_0->spr[SPR_BOOKE_EPR] = VAR_2.u.e.epr;

        }



        if (VAR_2.u.e.features & KVM_SREGS_E_PD) {

            VAR_0->spr[SPR_BOOKE_EPLC] = VAR_2.u.e.eplc;

            VAR_0->spr[SPR_BOOKE_EPSC] = VAR_2.u.e.epsc;

        }



        if (VAR_2.u.e.impl_id == KVM_SREGS_E_IMPL_FSL) {

            VAR_0->spr[SPR_E500_SVR] = VAR_2.u.e.impl.fsl.svr;

            VAR_0->spr[SPR_Exxx_MCAR] = VAR_2.u.e.impl.fsl.mcar;

            VAR_0->spr[SPR_HID0] = VAR_2.u.e.impl.fsl.hid0;



            if (VAR_2.u.e.impl.fsl.features & KVM_SREGS_E_FSL_PIDn) {

                VAR_0->spr[SPR_BOOKE_PID1] = VAR_2.u.e.impl.fsl.pid1;

                VAR_0->spr[SPR_BOOKE_PID2] = VAR_2.u.e.impl.fsl.pid2;

            }

        }

    }

#endif



#ifdef KVM_CAP_PPC_SEGSTATE

    if (cap_segstate) {

        VAR_4 = kvm_vcpu_ioctl(VAR_0, KVM_GET_SREGS, &VAR_2);

        if (VAR_4 < 0) {

            return VAR_4;

        }



        ppc_store_sdr1(VAR_0, VAR_2.u.s.sdr1);



        

#ifdef TARGET_PPC64

        for (VAR_3 = 0; VAR_3 < 64; VAR_3++) {

            ppc_store_slb(VAR_0, VAR_2.u.s.ppc64.slb[VAR_3].slbe,

                               VAR_2.u.s.ppc64.slb[VAR_3].slbv);

        }

#endif



        

        for (VAR_3 = 0; VAR_3 < 16; VAR_3++) {

            VAR_0->sr[VAR_3] = VAR_2.u.s.ppc32.sr[VAR_3];

        }



        

        for (VAR_3 = 0; VAR_3 < 8; VAR_3++) {

            VAR_0->DBAT[0][VAR_3] = VAR_2.u.s.ppc32.dbat[VAR_3] & 0xffffffff;

            VAR_0->DBAT[1][VAR_3] = VAR_2.u.s.ppc32.dbat[VAR_3] >> 32;

            VAR_0->IBAT[0][VAR_3] = VAR_2.u.s.ppc32.ibat[VAR_3] & 0xffffffff;

            VAR_0->IBAT[1][VAR_3] = VAR_2.u.s.ppc32.ibat[VAR_3] >> 32;

        }

    }

#endif



    return 0;

}

int FUNC_0(CPUState *VAR_0)
{ struct kvm_regs VAR_1; struct kvm_sregs VAR_2; uint32_t cr; int VAR_3, VAR_4; VAR_4 = kvm_vcpu_ioctl(VAR_0, KVM_GET_REGS, &VAR_1); if (VAR_4 < 0)
return VAR_4; cr = VAR_1.cr; for (VAR_3 = 7; VAR_3 >= 0; VAR_3--) { VAR_0->crf[VAR_3] = cr & 15; cr >>= 4; } VAR_0->ctr = VAR_1.ctr; VAR_0->lr = VAR_1.lr; VAR_0->xer = VAR_1.xer; VAR_0->msr = VAR_1.msr; VAR_0->nip = VAR_1.pc; VAR_0->spr[SPR_SRR0] = VAR_1.srr0; VAR_0->spr[SPR_SRR1] = VAR_1.srr1; VAR_0->spr[SPR_SPRG0] = VAR_1.sprg0; VAR_0->spr[SPR_SPRG1] = VAR_1.sprg1; VAR_0->spr[SPR_SPRG2] = VAR_1.sprg2; VAR_0->spr[SPR_SPRG3] = VAR_1.sprg3; VAR_0->spr[SPR_SPRG4] = VAR_1.sprg4; VAR_0->spr[SPR_SPRG5] = VAR_1.sprg5; VAR_0->spr[SPR_SPRG6] = VAR_1.sprg6; VAR_0->spr[SPR_SPRG7] = VAR_1.sprg7; VAR_0->spr[SPR_BOOKE_PID] = VAR_1.pid; for (VAR_3 = 0;VAR_3 < 32; VAR_3++) VAR_0->gpr[VAR_3] = VAR_1.gpr[VAR_3]; #ifdef KVM_CAP_PPC_BOOKE_SREGS
if (cap_booke_sregs) { VAR_4 = kvm_vcpu_ioctl(VAR_0, KVM_GET_SREGS, &VAR_2); if (VAR_4 < 0) { return VAR_4; } if (VAR_2.u.e.features & KVM_SREGS_E_BASE) { VAR_0->spr[SPR_BOOKE_CSRR0] = VAR_2.u.e.csrr0; VAR_0->spr[SPR_BOOKE_CSRR1] = VAR_2.u.e.csrr1; VAR_0->spr[SPR_BOOKE_ESR] = VAR_2.u.e.esr; VAR_0->spr[SPR_BOOKE_DEAR] = VAR_2.u.e.dear; VAR_0->spr[SPR_BOOKE_MCSR] = VAR_2.u.e.mcsr; VAR_0->spr[SPR_BOOKE_TSR] = VAR_2.u.e.tsr; VAR_0->spr[SPR_BOOKE_TCR] = VAR_2.u.e.tcr; VAR_0->spr[SPR_DECR] = VAR_2.u.e.dec; VAR_0->spr[SPR_TBL] = VAR_2.u.e.tb & 0xffffffff; VAR_0->spr[SPR_TBU] = VAR_2.u.e.tb >> 32; VAR_0->spr[SPR_VRSAVE] = VAR_2.u.e.vrsave; } if (VAR_2.u.e.features & KVM_SREGS_E_ARCH206) { VAR_0->spr[SPR_BOOKE_PIR] = VAR_2.u.e.pir; VAR_0->spr[SPR_BOOKE_MCSRR0] = VAR_2.u.e.mcsrr0; VAR_0->spr[SPR_BOOKE_MCSRR1] = VAR_2.u.e.mcsrr1; VAR_0->spr[SPR_BOOKE_DECAR] = VAR_2.u.e.decar; VAR_0->spr[SPR_BOOKE_IVPR] = VAR_2.u.e.ivpr; } if (VAR_2.u.e.features & KVM_SREGS_E_64) { VAR_0->spr[SPR_BOOKE_EPCR] = VAR_2.u.e.epcr; } if (VAR_2.u.e.features & KVM_SREGS_E_SPRG8) { VAR_0->spr[SPR_BOOKE_SPRG8] = VAR_2.u.e.sprg8; } if (VAR_2.u.e.features & KVM_SREGS_E_IVOR) { VAR_0->spr[SPR_BOOKE_IVOR0] = VAR_2.u.e.ivor_low[0]; VAR_0->spr[SPR_BOOKE_IVOR1] = VAR_2.u.e.ivor_low[1]; VAR_0->spr[SPR_BOOKE_IVOR2] = VAR_2.u.e.ivor_low[2]; VAR_0->spr[SPR_BOOKE_IVOR3] = VAR_2.u.e.ivor_low[3]; VAR_0->spr[SPR_BOOKE_IVOR4] = VAR_2.u.e.ivor_low[4]; VAR_0->spr[SPR_BOOKE_IVOR5] = VAR_2.u.e.ivor_low[5]; VAR_0->spr[SPR_BOOKE_IVOR6] = VAR_2.u.e.ivor_low[6]; VAR_0->spr[SPR_BOOKE_IVOR7] = VAR_2.u.e.ivor_low[7]; VAR_0->spr[SPR_BOOKE_IVOR8] = VAR_2.u.e.ivor_low[8]; VAR_0->spr[SPR_BOOKE_IVOR9] = VAR_2.u.e.ivor_low[9]; VAR_0->spr[SPR_BOOKE_IVOR10] = VAR_2.u.e.ivor_low[10]; VAR_0->spr[SPR_BOOKE_IVOR11] = VAR_2.u.e.ivor_low[11]; VAR_0->spr[SPR_BOOKE_IVOR12] = VAR_2.u.e.ivor_low[12]; VAR_0->spr[SPR_BOOKE_IVOR13] = VAR_2.u.e.ivor_low[13]; VAR_0->spr[SPR_BOOKE_IVOR14] = VAR_2.u.e.ivor_low[14]; VAR_0->spr[SPR_BOOKE_IVOR15] = VAR_2.u.e.ivor_low[15]; if (VAR_2.u.e.features & KVM_SREGS_E_SPE) { VAR_0->spr[SPR_BOOKE_IVOR32] = VAR_2.u.e.ivor_high[0]; VAR_0->spr[SPR_BOOKE_IVOR33] = VAR_2.u.e.ivor_high[1]; VAR_0->spr[SPR_BOOKE_IVOR34] = VAR_2.u.e.ivor_high[2]; } if (VAR_2.u.e.features & KVM_SREGS_E_PM) { VAR_0->spr[SPR_BOOKE_IVOR35] = VAR_2.u.e.ivor_high[3]; } if (VAR_2.u.e.features & KVM_SREGS_E_PC) { VAR_0->spr[SPR_BOOKE_IVOR36] = VAR_2.u.e.ivor_high[4]; VAR_0->spr[SPR_BOOKE_IVOR37] = VAR_2.u.e.ivor_high[5]; } } if (VAR_2.u.e.features & KVM_SREGS_E_ARCH206_MMU) { VAR_0->spr[SPR_BOOKE_MAS0] = VAR_2.u.e.mas0; VAR_0->spr[SPR_BOOKE_MAS1] = VAR_2.u.e.mas1; VAR_0->spr[SPR_BOOKE_MAS2] = VAR_2.u.e.mas2; VAR_0->spr[SPR_BOOKE_MAS3] = VAR_2.u.e.mas7_3 & 0xffffffff; VAR_0->spr[SPR_BOOKE_MAS4] = VAR_2.u.e.mas4; VAR_0->spr[SPR_BOOKE_MAS6] = VAR_2.u.e.mas6; VAR_0->spr[SPR_BOOKE_MAS7] = VAR_2.u.e.mas7_3 >> 32; VAR_0->spr[SPR_MMUCFG] = VAR_2.u.e.mmucfg; VAR_0->spr[SPR_BOOKE_TLB0CFG] = VAR_2.u.e.tlbcfg[0]; VAR_0->spr[SPR_BOOKE_TLB1CFG] = VAR_2.u.e.tlbcfg[1]; } if (VAR_2.u.e.features & KVM_SREGS_EXP) { VAR_0->spr[SPR_BOOKE_EPR] = VAR_2.u.e.epr; } if (VAR_2.u.e.features & KVM_SREGS_E_PD) { VAR_0->spr[SPR_BOOKE_EPLC] = VAR_2.u.e.eplc; VAR_0->spr[SPR_BOOKE_EPSC] = VAR_2.u.e.epsc; } if (VAR_2.u.e.impl_id == KVM_SREGS_E_IMPL_FSL) { VAR_0->spr[SPR_E500_SVR] = VAR_2.u.e.impl.fsl.svr; VAR_0->spr[SPR_Exxx_MCAR] = VAR_2.u.e.impl.fsl.mcar; VAR_0->spr[SPR_HID0] = VAR_2.u.e.impl.fsl.hid0; if (VAR_2.u.e.impl.fsl.features & KVM_SREGS_E_FSL_PIDn) { VAR_0->spr[SPR_BOOKE_PID1] = VAR_2.u.e.impl.fsl.pid1; VAR_0->spr[SPR_BOOKE_PID2] = VAR_2.u.e.impl.fsl.pid2; } } } #endif
#ifdef KVM_CAP_PPC_SEGSTATE
if (cap_segstate) { VAR_4 = kvm_vcpu_ioctl(VAR_0, KVM_GET_SREGS, &VAR_2); if (VAR_4 < 0) { return VAR_4; } ppc_store_sdr1(VAR_0, VAR_2.u.s.sdr1); #ifdef TARGET_PPC64
for (VAR_3 = 0; VAR_3 < 64; VAR_3++) { ppc_store_slb(VAR_0, VAR_2.u.s.ppc64.slb[VAR_3].slbe,
VAR_2.u.s.ppc64.slb[VAR_3].slbv); } #endif
for (VAR_3 = 0; VAR_3 < 16; VAR_3++) { VAR_0->sr[VAR_3] = VAR_2.u.s.ppc32.sr[VAR_3]; } for (VAR_3 = 0; VAR_3 < 8; VAR_3++) { VAR_0->DBAT[0][VAR_3] = VAR_2.u.s.ppc32.dbat[VAR_3] & 0xffffffff; VAR_0->DBAT[1][VAR_3] = VAR_2.u.s.ppc32.dbat[VAR_3] >> 32; VAR_0->IBAT[0][VAR_3] = VAR_2.u.s.ppc32.ibat[VAR_3] & 0xffffffff; VAR_0->IBAT[1][VAR_3] = VAR_2.u.s.ppc32.ibat[VAR_3] >> 32; } } #endif
return 0; }