static void omap_dpll_write(void *opaque, target_phys_addr_t addr,

                            uint64_t value, unsigned size)

{

    struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque;

    uint16_t diff;

    static const int bypass_div[4] = { 1, 2, 4, 4 };

    int div, mult;



    if (size != 2) {

        return omap_badwidth_write16(opaque, addr, value);

    }



    if (addr == 0x00) {	/* CTL_REG */

        /* See omap_ulpd_pm_write() too */

        diff = s->mode & value;

        s->mode = value & 0x2fff;

        if (diff & (0x3ff << 2)) {

            if (value & (1 << 4)) {			/* PLL_ENABLE */

                div = ((value >> 5) & 3) + 1;		/* PLL_DIV */

                mult = MIN((value >> 7) & 0x1f, 1);	/* PLL_MULT */

            } else {

                div = bypass_div[((value >> 2) & 3)];	/* BYPASS_DIV */

                mult = 1;

            }

            omap_clk_setrate(s->dpll, div, mult);

        }



        /* Enter the desired mode.  */

        s->mode = (s->mode & 0xfffe) | ((s->mode >> 4) & 1);



        /* Act as if the lock is restored.  */

        s->mode |= 2;

    } else {

        OMAP_BAD_REG(addr);

    }

}

static void omap_dpll_write(void *opaque, target_phys_addr_t addr,

                            uint64_t value, unsigned size)

{

    struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque;

    uint16_t diff;

    static const int bypass_div[4] = { 1, 2, 4, 4 };

    int div, mult;



    if (size != 2) {

        return omap_badwidth_write16(opaque, addr, value);

    }



    if (addr == 0x00) {	

        

        diff = s->mode & value;

        s->mode = value & 0x2fff;

        if (diff & (0x3ff << 2)) {

            if (value & (1 << 4)) {			

                div = ((value >> 5) & 3) + 1;		

                mult = MIN((value >> 7) & 0x1f, 1);	

            } else {

                div = bypass_div[((value >> 2) & 3)];	

                mult = 1;

            }

            omap_clk_setrate(s->dpll, div, mult);

        }



        

        s->mode = (s->mode & 0xfffe) | ((s->mode >> 4) & 1);



        

        s->mode |= 2;

    } else {

        OMAP_BAD_REG(addr);

    }

}

static void FUNC_0(void *VAR_0, target_phys_addr_t VAR_1,

                            uint64_t VAR_2, unsigned VAR_3)

{

    struct dpll_ctl_s *VAR_4 = (struct dpll_ctl_s *) VAR_0;

    uint16_t diff;

    static const int VAR_5[4] = { 1, 2, 4, 4 };

    int VAR_6, VAR_7;



    if (VAR_3 != 2) {

        return omap_badwidth_write16(VAR_0, VAR_1, VAR_2);

    }



    if (VAR_1 == 0x00) {	

        

        diff = VAR_4->mode & VAR_2;

        VAR_4->mode = VAR_2 & 0x2fff;

        if (diff & (0x3ff << 2)) {

            if (VAR_2 & (1 << 4)) {			

                VAR_6 = ((VAR_2 >> 5) & 3) + 1;		

                VAR_7 = MIN((VAR_2 >> 7) & 0x1f, 1);	

            } else {

                VAR_6 = VAR_5[((VAR_2 >> 2) & 3)];	

                VAR_7 = 1;

            }

            omap_clk_setrate(VAR_4->dpll, VAR_6, VAR_7);

        }



        

        VAR_4->mode = (VAR_4->mode & 0xfffe) | ((VAR_4->mode >> 4) & 1);



        

        VAR_4->mode |= 2;

    } else {

        OMAP_BAD_REG(VAR_1);

    }

}

static void FUNC_0(void *VAR_0, target_phys_addr_t VAR_1,
uint64_t VAR_2, unsigned VAR_3)
{ struct dpll_ctl_s *VAR_4 = (struct dpll_ctl_s *) VAR_0; uint16_t diff; static const int VAR_5[4] = { 1, 2, 4, 4 }; int VAR_6, VAR_7; if (VAR_3 != 2) { return omap_badwidth_write16(VAR_0, VAR_1, VAR_2); } if (VAR_1 == 0x00) { diff = VAR_4->mode & VAR_2; VAR_4->mode = VAR_2 & 0x2fff; if (diff & (0x3ff << 2)) { if (VAR_2 & (1 << 4)) { VAR_6 = ((VAR_2 >> 5) & 3) + 1; VAR_7 = MIN((VAR_2 >> 7) & 0x1f, 1); } else { VAR_6 = VAR_5[((VAR_2 >> 2) & 3)]; VAR_7 = 1; } omap_clk_setrate(VAR_4->dpll, VAR_6, VAR_7); } VAR_4->mode = (VAR_4->mode & 0xfffe) | ((VAR_4->mode >> 4) & 1); VAR_4->mode |= 2; } else { OMAP_BAD_REG(VAR_1); } }