static void cg3_reg_write(void *opaque, hwaddr addr, uint64_t val,

                          unsigned size)

{

    CG3State *s = opaque;

    uint8_t regval;

    int i;



    DPRINTF("write %" PRIx64 " to reg %" HWADDR_PRIx " size %d\n",

            val, addr, size);



    switch (addr) {

    case CG3_REG_BT458_ADDR:

        s->dac_index = val;

        s->dac_state = 0;

        break;

    case CG3_REG_BT458_COLMAP:

        /* This register can be written to as either a long word or a byte */

        if (size == 1) {

            val <<= 24;

        }



        for (i = 0; i < size; i++) {

            regval = val >> 24;



            switch (s->dac_state) {

            case 0:

                s->r[s->dac_index] = regval;

                s->dac_state++;

                break;

            case 1:

                s->g[s->dac_index] = regval;

                s->dac_state++;

                break;

            case 2:

                s->b[s->dac_index] = regval;

                /* Index autoincrement */

                s->dac_index = (s->dac_index + 1) & 0xff;

            default:

                s->dac_state = 0;

                break;

            }

            val <<= 8;

        }

        s->full_update = 1;

        break;

    case CG3_REG_FBC_CTRL:

        s->regs[0] = val;

        break;

    case CG3_REG_FBC_STATUS:

        if (s->regs[1] & CG3_SR_PENDING_INT) {

            /* clear interrupt */

            s->regs[1] &= ~CG3_SR_PENDING_INT;

            qemu_irq_lower(s->irq);

        }

        break;

    case CG3_REG_FBC_CURSTART ... CG3_REG_SIZE:

        s->regs[addr - 0x10] = val;

        break;

    default:

        qemu_log_mask(LOG_UNIMP,

                  "cg3: Unimplemented register write "

                  "reg 0x%" HWADDR_PRIx " size 0x%x value 0x%" PRIx64 "\n",

                  addr, size, val);

        break;

    }

}

static void cg3_reg_write(void *opaque, hwaddr addr, uint64_t val,

                          unsigned size)

{

    CG3State *s = opaque;

    uint8_t regval;

    int i;



    DPRINTF("write %" PRIx64 " to reg %" HWADDR_PRIx " size %d\n",

            val, addr, size);



    switch (addr) {

    case CG3_REG_BT458_ADDR:

        s->dac_index = val;

        s->dac_state = 0;

        break;

    case CG3_REG_BT458_COLMAP:

        

        if (size == 1) {

            val <<= 24;

        }



        for (i = 0; i < size; i++) {

            regval = val >> 24;



            switch (s->dac_state) {

            case 0:

                s->r[s->dac_index] = regval;

                s->dac_state++;

                break;

            case 1:

                s->g[s->dac_index] = regval;

                s->dac_state++;

                break;

            case 2:

                s->b[s->dac_index] = regval;

                

                s->dac_index = (s->dac_index + 1) & 0xff;

            default:

                s->dac_state = 0;

                break;

            }

            val <<= 8;

        }

        s->full_update = 1;

        break;

    case CG3_REG_FBC_CTRL:

        s->regs[0] = val;

        break;

    case CG3_REG_FBC_STATUS:

        if (s->regs[1] & CG3_SR_PENDING_INT) {

            

            s->regs[1] &= ~CG3_SR_PENDING_INT;

            qemu_irq_lower(s->irq);

        }

        break;

    case CG3_REG_FBC_CURSTART ... CG3_REG_SIZE:

        s->regs[addr - 0x10] = val;

        break;

    default:

        qemu_log_mask(LOG_UNIMP,

                  "cg3: Unimplemented register write "

                  "reg 0x%" HWADDR_PRIx " size 0x%x value 0x%" PRIx64 "\n",

                  addr, size, val);

        break;

    }

}

    case CG3_REG_FBC_CURSTART ... CG3_REG_SIZE:     case CG3_REG_FBC_CURSTART ... CG3_REG_SIZE:
static void FUNC_0(void *VAR_0, hwaddr VAR_1, uint64_t VAR_2,

                          unsigned VAR_3)

{

    CG3State *s = VAR_0;

    uint8_t regval;

    int VAR_4;



    DPRINTF("write %" PRIx64 " to reg %" HWADDR_PRIx " VAR_3 %d\n",

            VAR_2, VAR_1, VAR_3);



    switch (VAR_1) {

    case CG3_REG_BT458_ADDR:

        s->dac_index = VAR_2;

        s->dac_state = 0;

        break;

    case CG3_REG_BT458_COLMAP:

        

        if (VAR_3 == 1) {

            VAR_2 <<= 24;

        }



        for (VAR_4 = 0; VAR_4 < VAR_3; VAR_4++) {

            regval = VAR_2 >> 24;



            switch (s->dac_state) {

            case 0:

                s->r[s->dac_index] = regval;

                s->dac_state++;

                break;

            case 1:

                s->g[s->dac_index] = regval;

                s->dac_state++;

                break;

            case 2:

                s->b[s->dac_index] = regval;

                

                s->dac_index = (s->dac_index + 1) & 0xff;

            default:

                s->dac_state = 0;

                break;

            }

            VAR_2 <<= 8;

        }

        s->full_update = 1;

        break;

    case CG3_REG_FBC_CTRL:

        s->regs[0] = VAR_2;

        break;

    case CG3_REG_FBC_STATUS:

        if (s->regs[1] & CG3_SR_PENDING_INT) {

            

            s->regs[1] &= ~CG3_SR_PENDING_INT;

            qemu_irq_lower(s->irq);

        }

        break;

    case CG3_REG_FBC_CURSTART ... CG3_REG_SIZE:

        s->regs[VAR_1 - 0x10] = VAR_2;

        break;

    default:

        qemu_log_mask(LOG_UNIMP,

                  "cg3: Unimplemented register write "

                  "reg 0x%" HWADDR_PRIx " VAR_3 0x%x value 0x%" PRIx64 "\n",

                  VAR_1, VAR_3, VAR_2);

        break;

    }

}

static void FUNC_0(void *VAR_0, hwaddr VAR_1, uint64_t VAR_2,
unsigned VAR_3)
{ CG3State *s = VAR_0; uint8_t regval; int VAR_4; DPRINTF("write %" PRIx64 " to reg %" HWADDR_PRIx " VAR_3 %d\n",
VAR_2, VAR_1, VAR_3); switch (VAR_1) { case CG3_REG_BT458_ADDR:
s->dac_index = VAR_2; s->dac_state = 0; break; case CG3_REG_BT458_COLMAP:
if (VAR_3 == 1) { VAR_2 <<= 24; } for (VAR_4 = 0; VAR_4 < VAR_3; VAR_4++) { regval = VAR_2 >> 24; switch (s->dac_state) { case 0:
s->r[s->dac_index] = regval; s->dac_state++; break; case 1:
s->g[s->dac_index] = regval; s->dac_state++; break; case 2:
s->b[s->dac_index] = regval; s->dac_index = (s->dac_index + 1) & 0xff; default:
s->dac_state = 0; break; } VAR_2 <<= 8; } s->full_update = 1; break; case CG3_REG_FBC_CTRL:
s->regs[0] = VAR_2; break; case CG3_REG_FBC_STATUS:
if (s->regs[1] & CG3_SR_PENDING_INT) { s->regs[1] &= ~CG3_SR_PENDING_INT; qemu_irq_lower(s->irq); } break; case CG3_REG_FBC_CURSTART ... CG3_REG_SIZE:
s->regs[VAR_1 - 0x10] = VAR_2; break; default:
qemu_log_mask(LOG_UNIMP,
"cg3: Unimplemented register write "
"reg 0x%" HWADDR_PRIx " VAR_3 0x%x value 0x%" PRIx64 "\n",
VAR_1, VAR_3, VAR_2); break; } }