static void trigger_prot_fault(CPUS390XState *env, target_ulong vaddr,

                               uint64_t mode)

{

    CPUState *cs = CPU(s390_env_get_cpu(env));

    int ilen = ILEN_LATER_INC;

    int bits = trans_bits(env, mode) | 4;



    DPRINTF("%s: vaddr=%016" PRIx64 " bits=%d\n", __func__, vaddr, bits);



    stq_phys(cs->as,

             env->psa + offsetof(LowCore, trans_exc_code), vaddr | bits);

    trigger_pgm_exception(env, PGM_PROTECTION, ilen);

}

static void trigger_prot_fault(CPUS390XState *env, target_ulong vaddr,

                               uint64_t mode)

{

    CPUState *cs = CPU(s390_env_get_cpu(env));

    int ilen = ILEN_LATER_INC;

    int bits = trans_bits(env, mode) | 4;



    DPRINTF("%s: vaddr=%016" PRIx64 " bits=%d\n", __func__, vaddr, bits);



    stq_phys(cs->as,

             env->psa + offsetof(LowCore, trans_exc_code), vaddr | bits);

    trigger_pgm_exception(env, PGM_PROTECTION, ilen);

}

static void FUNC_0(CPUS390XState *VAR_0, target_ulong VAR_1,

                               uint64_t VAR_2)

{

    CPUState *cs = CPU(s390_env_get_cpu(VAR_0));

    int VAR_3 = ILEN_LATER_INC;

    int VAR_4 = trans_bits(VAR_0, VAR_2) | 4;



    DPRINTF("%s: VAR_1=%016" PRIx64 " VAR_4=%d\n", __func__, VAR_1, VAR_4);



    stq_phys(cs->as,

             VAR_0->psa + offsetof(LowCore, trans_exc_code), VAR_1 | VAR_4);

    trigger_pgm_exception(VAR_0, PGM_PROTECTION, VAR_3);

}

static void FUNC_0(CPUS390XState *VAR_0, target_ulong VAR_1,
uint64_t VAR_2)
{ CPUState *cs = CPU(s390_env_get_cpu(VAR_0)); int VAR_3 = ILEN_LATER_INC; int VAR_4 = trans_bits(VAR_0, VAR_2) | 4; DPRINTF("%s: VAR_1=%016" PRIx64 " VAR_4=%d\n", __func__, VAR_1, VAR_4); stq_phys(cs->as,
VAR_0->psa + offsetof(LowCore, trans_exc_code), VAR_1 | VAR_4); trigger_pgm_exception(VAR_0, PGM_PROTECTION, VAR_3); }