The Alpha 21164, also known by its code name, EV5, is a microprocessor developed and fabricated by Digital Equipment Corporation that implemented the Alpha instruction set architecture (ISA). It was introduced in January 1995, succeeding the Alpha 21064A as Digital's flagship microprocessor. It was succeeded by the Alpha 21264 in 1998.

History
First silicon of the Alpha 21164 was produced in February 1994, and the OpenVMS, Digital UNIX and Windows NT operating systems were successfully booted on it. It was sampled in late 1994 and was introduced in January 1995 at 266 MHz. A 300 MHz version was introduced in March 1995. The final Alpha 21164, a 333 MHz version, was announced on 2 October 1995, available in sample quantities. The Alpha 21164 was replaced by the Alpha 21164A as Digital's flagship microprocessor in 1996 when a 400 MHz version became available in volume quantities.

Users
Digital used the Alpha 21164 operating at various clock frequencies in their AlphaServer servers, AlphaStation workstations. Digital also used the Alpha 21164 in their Alpha VME 5/352 and Alpha VME 5/480 single board computers and AlphaPC 164 and AlphaPC 164LX motherboards. Alpha partner Cray Research used a 300 MHz Alpha 21164 in their T3E-600 supercomputer. Third parties such as DeskStation also built workstations using the Alpha 21164.

Performance
The 21164 continued the performance lead from the 275 MHz Alpha 21064A until the introduction of the Intel Pentium Pro in November 1995, when a 200 MHz version outperformed the 300 MHz 21164 on the SPECint95_base benchmark suite. The 21164 retained its floating-point performance lead. The 333 MHz 21164 introduce the following year outperformed the Pentium Pro, but it was later surpassed by the MIPS Technologies R10000 and then by the Hewlett-Packard PA-8000 in the same year.

Description
The Alpha 21164 is a four-issue superscalar microprocessor capable of issuing a maximum of four instructions per clock cycle to four execution units: two integer and two floating-point. The integer pipeline is seven stages long, and the floating-point pipeline is ten stages long. The 21164 implemented a 43-bit virtual address and a 40-bit physical address. It was therefore capable of addressing 8 TB of virtual memory and 1 TB of physical memory.

Integer unit
The integer unit consisted of two integer pipelines and the integer register file. The two pipelines, the add pipeline and the multiply pipeline are not identical, each are responsible for executing different instructions, although both are capable of executing common add, logical, load, compare, and conditional move instructions. The multiply pipeline exclusively executes shift, store, and multiply instructions (in a non-pipelined multiplier). The add pipeline exclusively executes branch instructions.

Except for branch, conditional move, and multiply instructions, all other instructions begin and finish execution during stage five for a one cycle latency. Branch and conditional move instructions are executed during stage six so they can be issued with a compare instruction whose result they depend on.

The integer register file contained forty 64-bit registers, of which thirty-two are specified by the Alpha Architecture and eight are for use by PALcode as scratchpad memory. The register file has four read ports and two write ports evenly divided between the two integer pipelines.

Floating-point unit
The floating-point unit consisted of two floating-point pipelines and the floating point register file. The two pipelines are not identical, one executed all floating-point instructions except for multiply, and the other executed only multiply instructions. Both pipelines have four stages. A non-pipelined floating-point divider is connected to the add pipeline. All floating-point instructions except for divide have four-cycle latency. Divides have variable latency that depends on whether the operation is being performed on single or on double precision floating-point numbers and numbers. Including overhead, single precision divides have a 15- to 31-cycle latency, whereas double precision divides have a 22- to 60-cycle latency.

Cache
The 21164 has three levels of cache, two on-die and one external and optional. The caches and the associated logic consisted of 7.2 million transistors.

The primary cache is split into separate caches for instructions and data, referred to as the I-cache and D-cache respectively. They are 8 KB in size, direct-mapped and have a cache line size of 32 bytes. The D-cache is dual-ported, to improve performance, and is implemented by duplicating the cache twice. It uses a write-through write policy and an on-read allocation policy.

The secondary cache, known as the S-cache, is on-die and has a capacity of 96 KB. An on-die secondary cache was required as the 21164 required more bandwidth than an external secondary cache could supply in order to provide it with enough instructions and data. The cache required two cycles to access due to its large area. To improve performance, the cache is pipelined. Another benefit of an on-die secondary cache was that it could be easily implemented as a multi-way cache, and as a result, the cache is three-way set associative, offering improved hit rates than direct-mapped caches. The S-cache, due to the large physical area required, was implemented in two halves which flank the I-box, E-box, F-box and M-box. This was done so the cache could return data in two cycles.

The tertiary cache, known as the B-cache, is implemented with external SRAMs. The B-cache was optional and some systems using the Alpha 21164 did not have any. The B-cache could have a capacity of 1 to 64 MB, smaller capacities were not supported as they were rendered useless by the on-die S-cache. It is direct-mapped, uses a write-back write policy and an on-write allocation policy. The B-cache is controlled by on-die external interface logic, unlike the 21064, which required an external cache controller. The B-cache could be built with asynchronous or synchronous SRAMs. The B-cache is accessed via the system bus.

External interface

The external interface is a 128-bit system bus. The system bus operates at a clock frequency that is 3 to 15 times lower than the internal clock frequency, or 20 to 100 MHz with an internal clock frequency 300 MHz. The system bus' clock signal is generated by the microprocessor.

Clock
The internal clock frequency is generated by dividing an external clock signal by two. The Alpha 21164 therefore requires an external clock signal of 600 MHz for a 300 MHz Alpha 21164.

Fabrication
The Alpha 21164 contains 9.3 million transistors on a die measuring 16.5 by 18.1 mm (299 mm2), which was close to the maximum limits of the process. The die was fabricated in Digital's fifth-generation complementary metal–oxide–semiconductor (CMOS) process, CMOS-5, a 0.50 μm process with four levels of aluminium interconnect. The 21164 used a 3.3-volt (V) power supply. It dissipated 46 W at 266 MHz, 51 W at 300 MHz, 56 W at 333 MHz.

Package
The Alpha 21164 is packaged in a 499-pin ceramic interstitial pin grid array (IPGA) measuring 57.40 by 57.40 mm. The package had a heat spreader with two studs to which the heat sink was bolted.

Derivatives

Alpha 21164 (EV56)

The Alpha 21164 was the basis of a further development code-named EV56. It was introduced as the Alpha 21164, but was originally known as the Alpha 21164A. It operated at clock frequencies of 366, 433, 500, 533, 566, 600 and 666 MHz.

History
It was first described in October 1995 at the Microprocessor Forum. On 13 November 1995, Digital announced that samples would ship later in the month. The first version, operating at 366 MHz, was introduced in 1996. On 8 July 1996, Digital announced that a 433 MHz version was available and a 500 MHz version was sampling with volume quantities due in September 1996. The 433 MHz version was priced at $1,492 per unit in quantities of 1,000. The 600 MHz version was introduced on 31 March 1997, shipping in volume quantities. Samsung Electronics signed a deal with Digital in June 1996 to second source the Alpha 21164A and the company was the only one to fabricate the 666 MHz model. 366 to 500 MHz samples were introduced on 11 November 1996 with volume availability in 1997. The Alpha 21164A was fabricated at Digital's Hudson, Massachusetts and Samsung's Kihueng, South Korea fabrication plants.

Users of the Alpha 21164A included Cray Research, Digital, Network Appliance (now NetApp), and DeskStation. Cray Research used 450, 600 and 675 MHz Alpha 21164As in later models of their T3E supercomputer. Digital used the Alpha 21164A operating at various clock frequencies in their AlphaServers, AlphaStations, Celebris XL workstations and Digital Personal Workstations. NetApp used 400, 500 and 600 MHz Alpha 21164As in their storage systems. DeskStation used the Alpha 21164A in their Raptor Reflex workstations.

Description
The most notable change was the inclusion of Byte Word Extensions (BWX), an extension to the Alpha Architecture designed to improve byte and word accesses. These instructions are executed by the multiply pipeline. The Alpha 21164A contained 9.66 million transistors on a die measuring 14.4 mm by 14.5 mm, for a die area of 209 mm2. Digital fabricated the die in their sixth generation CMOS process, CMOS-6, a 0.35 μm process with four layers of interconnect. Samsung fabricated the die in their 0.35 μm process with four layers of interconnect based on a 0.3 μm process they developed in early 1996. The Alpha 21164A used a 3.3 V power supply, dissipating 31.0 W at 366 MHz, 36.0 W at 433 MHz, 41.0 W at 500 MHz, 43.5 W at 533 MHz and 48.5 W at 600 MHz.

Alpha 21164PC (PCA56)
The Alpha 21164PC, also known as the PCA56, is a low-cost version of the Alpha 21164A introduced on 17 March 1997. The microprocessor was jointly developed by Digital and Mitsubishi Electric Corporation, and both companies fabricated the design. Mitsubishi later suspended the joint development agreement for future Alpha microprocessors with Digital in early 1998 and ceased to fabricate the Alpha 21164PC in mid-1998, exited the Alpha market because the economic conditions in the company's markets.

The Alpha 21164PC operated at clock frequencies of 400, 466 and 533 MHz. Major changes are the omission of the S-cache, a larger I-cache, and the inclusion of Motion Video Instructions (MVI), an extension to the Alpha Architecture which introduced single instruction multiple data (SIMD) instructions for improving the performance of MPEG encoding. The S-cache was removed to reduce the transistor count, which reduced the die size and in turn, cost. The I-cache was doubled in capacity to 16 KB from 8 KB to compensate for the lack of S-cache, as the Alpha 21164 relied on the S-cache to complement the I-cache in order to provide enough bandwidth to achieve adequate performance. The amount of B-cache was limited to 512 KB to 4 MB, with 1 and 2 MB capacities also supported. The microprocessor uses a 43-bit virtual address and 33-bit physical address.

The Alpha 21164PC contained 3.5 million transistors on a die measuring 8.65 by 16.28 mm, for a die area of 141 mm2. Digital fabricated the die in the same process as the Alpha 21164, CMOS-5. The Alpha 21164PC was packaged in 413-pin IPGA measuring 49.78 by 49.78 mm. It used a 3.3 V power supply, dissipating 26.5 W at 400 MHz, 30.5 W at 466 MHz and 35.0 W at 533 MHz.

The Alpha 21164PC was used by Digital in their AlphaPC 164SX motherboard.

Alpha 21164PC (PCA57)
A derivative of the PCA56, the PCA57 was designed and fabricated by Samsung Electronics in a 0.28 μm CMOS process. The PCA57 was introduced in late 1998 and operated at clock frequencies of 533, 600 and 666 MHz. Improvements to the PCA56 microarchitecture included doubled I-cache and D-cache capacities: 32 KB and 16 KB respectively. The PCA57 contained 5.7 million transistors on a die measuring 6.7 mm by 15 mm, for a die area of 101 mm2. It operated on a 2.5 V power supply and dissipated 18 W at 533 MHz, 20 W at 600 MHz and 23 W at 666 MHz.

The PCA57 was used by Digital in its AlphaPC 164RX motherboard.

Chipsets
Digital and VLSI Technology developed chipsets for the 21164 and its derivatives. Digital also developed custom application-specific integrated circuit (ASICs) for use in the high-end models of their AlphaServer family such as the AlphaServer 8200 and 8400.

21171
The 21171, also known as Alcor, was the first chipset for the 21164, introduced in January 1995 alongside the microprocessor it supports. It was developed and fabricated by Digital. The 21171 is an upgraded DECchip 21071 modified to support the new system bus protocol the 21164 uses. It consisted of a control chip that contained the memory and PCI controllers, and four data slice chips that interfaced the 256-bit memory bus and PCI bus to the system bus. The 21171 provides a 64-bit wide PCI bus that runs at 33 MHz.

21172
The 21172, also known as Alcor2, was an updated 21171 that supported the 21164A.

Pyxis
The Pyxis chipset, also known as the 21174, supported the 21164A and 21164PC microprocessors. Unlike previous chipsets, it was designed for low-cost systems. As a result, it was a single-chip design packaged in a 474-contact ceramic ball grid array (CBGA) instead of multiple packages. It was subsequently used in cost-sensitive applications such as entry-level workstations (Digital Personal Workstation a-Series) and motherboards such as the AlphaPC 164LX and 164SX. When it was introduced, the 21174 was priced at US$142 in quantities of 1,000.

The 21174 contains a memory controller and PCI controller. The memory controller supported up to 512 MB of synchronous dynamic random access memory (SDRAM) and accesses it via a 128-bit memory bus. The memory can be either ECC or parity protected. The PCI controller provided a PCI or PCI-X bus.

Polaris
Polaris is a system controller developed by VLSI Technology for personal computers that supports the 21164A and 21164PC microprocessors. Polaris was announced on 16 June 1997. It supports up to 768 MB of EDO DRAM or up to 512 MB of SDRAM. The memory is accessed via a 128-bit bus. It provides a 32-bit, 33 MHz PCI bus for I/O.

Users of Polaris included Digital, for its AlphaPC 164RX motherboard.

Notes

References
 Bouchard, Gregg. "Design objectives of the 0.35 μm Alpha 21164 Microprocessor". IEEE Hot Chips Symposium, August 1996, IEEE Computer Society.
 Bowhill, William J. et al. (1995). "Circuit Implementation of a 300-MHz 64-bit Second-generation CMOS Alpha CPU". Digital Technical Journal, Volume 7, Number 1, pp. 100–118.
 Edmondson, John H. et al. (1995). "Internal Organization of the Alpha 21164, a 300-MHz 64-bit Quad-issue CMOS RISC Microprocessor". Digital Technical Journal, Volume 7, Number 1, 1995. pp. 119–135.
 Edmondson, John H. et al. (1995). "Superscalar Instruction Execution in the 21164 Alpha Microprocessor". IEEE Micro. pp. 33–43.
 Foremski, Tom (10 February 1998). "Mitsubishi steps back from Alpha". Electronics Weekly.
 Foremski, Tom (10 July 1998). "Mitsubishi Electric stops Alpha microprocessor manufacture". Electronics Weekly.
 Gwennap, Linley (12 September 1994). "Digital Leads the Pack with 21164". Microprocessor Report, Volume 8, Number 12.
 Gwennap, Linley (8 July 1996). "Digital's 21164 Reaches 500 MHz". Microprocessor Report, Volume 10, Number 9.
 Gwennap, Linley (31 March 1997). "Digital's 21164PC Aimed at PC Market". Microprocessor Report, Volume 11, Number 4.
 Ryan, Bob (October 1994). "Alpha Rides High". Byte.
 Samsung Semiconductor, Inc. (11 November 1996). "Samsung Introduces 500MHz Alpha 21164 Microprocessor; First product resulting from the Digital/Samsung licensing agreement to begin mass production by Q2 1997 ". Press release.
 Schumann, Reinhard C. (1997). "Design of the 21174 memory controller for Digital Personal Workstations" . Digital Technical Journal 9 (2): 57–70.
 VLSI Technology (16 June 1997). "Polaris, VLSI's New Alpha System Controller, Breaks the Gigabyte/Second Memory Transfer Barrier. End-Users Gain Full Performance on Alpha Systems". Press release.
 CCL Forums (25 March 1998). "DEC Alpha 566 vs. 600 MHz"

Further reading

 Bannon, P., Saito, Y. (1997). "The Alpha 21164PC microprocessor". Proceedings of Compcon '97, pp. 20–27.
 Bhandarkar, Dileep P. (1995). Alpha Architecture and Implementations. Digital Press.
 Carlson, D. et al. (1998). "A 667 MHz RISC microprocessor containing a 6.0 ns 64 b integer multiplier". ISSCC Digest of Technical Papers, pp. 294–295.
 Carlson, D.A.; Castelino, R.W.; Mueller, R.O. (November 1997). "Multimedia extensions for a 550-MHz RISC microprocessor". IEEE Journal of Solid-State Circuits 32 (11): pp. 1618–1624.
 Jain, A.K. et al. (1997). "1.38 cm2 550 MHz microprocessor with multimedia extensions". ISSCC Digest of Technical Papers, pp. 174–175, 451.
 Gronowski, Paul E. et al. (May 1998). "High-performance microprocessor design". IEEE Journal of Solid-State Circuits 33 (5): pp. 676–686.
 Kobayashi, S. et al. (1997). "A 550 MHz Alpha microprocessor targeted at PC applications". Proceedings of the 1997 International Symposium on VLSI Technology, Systems, and Applications, pp. 203–207.

External links
An Overview of the Alpha AXP 21164 Micro-Architecture, lecture by John Edmonson

DEC microprocessors
Superscalar microprocessors
64-bit microprocessors


The Alpha 21264 is a Digital Equipment Corporation RISC microprocessor launched on 19 October 1998. The 21264 implemented the Alpha instruction set architecture (ISA).

Description
The Alpha 21264 is a four-issue superscalar microprocessor with out-of-order execution and speculative execution. It has a peak execution rate of six instructions per cycle and could sustain four instructions per cycle. It has a seven-stage instruction pipeline.

Out of order execution
At any given stage, the microprocessor could have up to 80 instructions in various stages of execution, surpassing any other contemporary microprocessor.

Decoded instructions are held in instruction queues and are issued when their operands are available. The integer queue contained 20 entries and the floating-point queue 15. Each queue could issue as many instructions as there were pipelines.

Ebox
The Ebox executes integer, load and store instructions. It has two integer units, two load store units and two integer register files. Each integer register file contained 80 entries, of which 32 are architectural registers, 40 are rename registers and 8 are PAL shadow registers. There was no entry for register R31 because in the Alpha architecture, R31 is hardwired to zero and is read-only.

Each register file served an integer unit and a load store unit, and the register file and its two units are referred to as a "cluster". The two clusters were designated U0 and U1. This scheme was used as it reduced the number of write and read ports required to serve operands and receive results, thus reducing the physical size of the register file, enabling the microprocessor to operate at higher clock frequencies. Writes to any of the register files thus have to be synchronized, which required a clock cycle to complete, negatively impacting performance by one percent. The reduction of performance resulting from the synchronization was compensated in two ways. Firstly, the higher clock frequency achievable offset the loss. Secondly, the logic responsible for instruction issue avoided creating situations where the register file had to be synchronized by issuing instructions that were not dependent on data held in other register file where possible.

The clusters are near identical except for two differences: U1 has a seven-cycle pipelined multiplier while U0 has a three-cycle pipeline for executing Motion Video Instructions (MVI), an extension to the Alpha Architecture defining single instruction multiple data (SIMD) instructions for multimedia.

The load store units are simple arithmetic logic units used to calculate virtual addresses for memory access. They are also capable of executing simple arithmetic and logic instructions. The Alpha 21264 instruction issue logic utilized this capability, issuing instructions to these units when they were available for use (not performing address arithmetic).

The Ebox therefore has four 64-bit adders, four logic units, two barrel shifters, byte-manipulation logic, two sets of conditional branch logic equally divided between U1 and U0.

Fbox
The Fbox is responsible for executing floating-point instructions. It consists of two floating-point pipelines and a floating-point register file. The pipelines are not identical, one executes the majority of instructions and the other only multiply instructions. The adder pipeline has two non-pipelined units connected to it, a divide unit and a square root unit. Adds, multiplies and most other instructions have a 4-cycle latency, a double-precision divide has 16-cycle latency and a double-precision square root has a 33-cycle latency. The floating point register file contains 72 entries, of which 32 are architectural registers and 40 are rename registers.

Cache
The Alpha 21264 has two levels of cache, a primary cache and secondary cache. The level three (L3, or "victim") cache of the Alpha 21164 was not used due to problems with bandwidth.

Primary caches
The primary cache is split into separate caches for instructions and data ("modified Harvard architecture"), the I-cache and D-cache, respectively. Both caches have a capacity of 64 KB. The D-cache is dual-ported by transferring data on both the rising and falling edges of the clock signal. This method of dual-porting enabled any combination of reads or writes to the cache every processor cycle. It also avoided duplication the cache so there are two, as in the Alpha 21164. Duplicating the cache restricted the capacity of the cache, as it required more transistors to provide the same amount of capacity, and in turn increased the area required and power consumed.

B-cache
The secondary cache, termed the B-cache, is an external cache with a capacity of 1 to 16 MB. It is controlled by the microprocessor and is implemented by synchronous static random access memory (SSRAM) chips that operate at two thirds, half, one-third or one-fourth the internal clock frequency, or 133 to 333 MHz at 500 MHz. The B-cache was accessed with a dedicated 128-bit bus that operates at the same clock frequency as the SSRAM or at twice the clock frequency if double data rate SSRAM is used. The B-cache is direct-mapped.

Branch prediction
Branch prediction is performed by a tournament branch prediction algorithm. The algorithm was developed by Scott McFarling at Digital's Western Research Laboratory (WRL) and was described in a 1993 paper. This predictor was used as the Alpha 21264 has a minimum branch misprediction penalty of seven cycles. Due to the instruction cache's two cycle latency and the instruction queues, the average branch misprediction penalty is 11 cycles. The algorithm maintains two history tables, Local and Global, and the table used to predict the outcome of a branch is determined by a Choice predictor.

The local predictor is a two-level table which records the history of individual branches. It consists of a 1,024-entry by 10-bit branch history table. A two-level table was used as the prediction accuracy is similar to that of a larger single-level table while requiring fewer bits of storage. It has a 1,024-entry branch prediction table. Each entry is a 3-bit saturating counter. The value of the counter determines whether the current branch is taken or not taken.

The global predictor is a single-level, 4096-entry branch history table.  Each entry is a 2-bit saturating counter; the value of this counter determines whether the current branch is taken or not taken.

The choice predictor records the history of the local and global predictors to determine which predictor is the best for a particular branch. It has a 4,096-entry branch history table. Each entry is a 2-bit saturating counter. The value of the counter determines if the local or global predictor is used.

External interface
The external interface consisted of a bidirectional 64-bit double data rate (DDR) data bus and two 15-bit unidirectional time-multiplexed address and control buses, one for signals originating from the Alpha 21264 and one for signals originating from the system. Digital licensed the bus to Advanced Micro Devices (AMD), and it was subsequently used in their Athlon microprocessors, where it was known as the EV6 bus.

Memory addressing
Alpha 21264 CPU supports 48-bit or 43-bit virtual address (256 TiB or 8 TiB virtual address space respectively), selectable under IPR control (using VA_CTL control register). Alpha 21264 supports a 44-bit physical address (up to 16 TiB of physical memory). This is an increase from previous Alpha CPUs (43-bit virtual and 40-bit physical for Alpha 21164, and 43-bit virtual and 34-bit physical for Alpha 21064).

Fabrication
The Alpha 21264 contained 15.2 million transistors. The logic consisted of approximately six million transistors, with the rest contained in the caches and branch history tables. The die measured 16.7 mm by 18.8 mm (313.96 mm²). It was fabricated in a 0.35 μm complementary metal–oxide–semiconductor (CMOS) process with six levels of interconnect.

Packaging
The Alpha 21264 was packaged in a 587-pin ceramic interstitial pin grid array (IPGA).

Alpha Processor, Inc. later sold the Alpha 21264 in a Slot B package containing the microprocessor mounted on a printed circuit board with the B-cache and voltage regulators. The design was intended to use the success of slot-based microprocessors from Intel and AMD. Slot B was originally developed to be used by AMD's Athlon as well, so that API could obtain materials for the Slot B at commodity prices in order to reduce the cost of the Alpha 21264 to gain a wider market share. This never materialized as AMD chose to use Slot A for their slot-based Athlons.

Derivatives

Alpha 21264A

The Alpha 21264A, code-named EV67 was a shrink of the Alpha 21264 introduced in late 1999. There were six versions: 600, 667, 700, 733, 750, 833 MHz. The EV67 was the first Alpha microprocessor to implement the count extension (CIX), which extended the instruction set with instructions for performing population count. It was fabricated by Samsung Electronics in a 0.25 μm CMOS process that had 0.25 μm transistors but 0.35 μm metal layers. The die had an area of 210 mm². The EV68 used a 2.0 V power supply. It dissipated a maximum of 73 W at 600 MHz, 80 W at 667 MHz, 85 W at 700 MHz, 88 W at 733 MHz and 90 W at 750 MHz.

Alpha 21264B
The Alpha 21264B is a further development for increased clock frequencies. There were two models, one fabricated by IBM, code-named EV68C, and one by Samsung, code-named EV68A.

The EV68A was fabricated in a 0.18 μm CMOS process with aluminium interconnects. It had a die size of 125 mm², a third smaller than the Alpha 21264A, and used a 1.7 V power supply. It was available in volume in 2001 at clock frequencies of 750, 833, 875 and 940 MHz. The EV68A dissipated a maximum of 60 W at 750 MHz, 67 W at 833 MHz, 70 W at 875 MHz and 75 W at 940 MHz.

The EV68C was fabricated in a 0.18 μm CMOS process with copper interconnects. It was sampled in early 2000 and achieved a maximum clock frequency of 1.25 GHz.

In September 1998, Samsung announced they would fabricate a variant of the Alpha 21264B in a 0.18 μm fully depleted silicon-on-insulator (SOI) process with copper interconnects that was capable of achieving a clock frequency of 1.5 GHz. This version never materialized.

Alpha 21264C
The Alpha 21264C, code-named EV68CB was a derivative of the Alpha 21264. It was available at clock frequencies of 1.0, 1.25 and 1.33 GHz. The EV68CB contained 15.5 million transistors and measured 120 mm². It was fabricated by IBM in a 0.18 μm CMOS process with seven levels of copper interconnect and low-K dielectric. It was packaged in a 675-pad flip-chip ceramic land grid array (CLGA) measuring 49.53 by 49.53 mm. The EV68CB used a 1.7 V power supply, dissipating a maximum of 64 W at 1.0 GHz, 75 W at 1.25 GHz and 80 W at 1.33 GHz.

Alpha 21264D
The Alpha 21264D, code-named EV68CD is a faster derivative fabricated by IBM.

Alpha 21264E
The Alpha 21264E, code-named EV68E, was a cancelled derivative developed by Samsung first announced on 10 October 2000 at Microprocessor Forum 2000 slated for introduction at around mid-2001. Improvements were a higher operating frequency of 1.25 GHz and the addition of an on-die 1.85 MB secondary cache. It was to be fabricated in a 0.18 micrometre CMOS process with copper interconnects.

Chipsets
Digital and Advanced Micro Devices (AMD) both developed chipsets for the Alpha 21264.

21272/21274
The Digital 21272, also known as the Tsunami, and the 21274, also known as the Typhoon, were the first chipset for the Alpha 21264. The 21272 chipset supported one- or two-way multiprocessing and up to 8GB of memory, while the 21274 supported one-, two-, three- or four-way multiprocessing, up to 64GB of memory, and both supported one or two 64-bit 33 MHz PCI buses. They had 128- to 512-bit memory bus which operated at 83 MHz, yielding a maximum bandwidth of 5,312 MB/s. The chipset supported 100 MHz registered ECC SDRAM.

The chipset consisted of three devices, a C-chip, a D-chip and a P-chip. The number of devices which made up the chipset varied as it was determined by the configuration of the chipset. The C-chip is the control chip containing the memory controller. One C-chip was required for every microprocessor.

The P-chip is the PCI controller, implementing a 33 MHz PCI bus. The 21272 could have one or two P-chips.

The D-chip is the DRAM controller, implementing access to/from the CPUs, and to/from the P-chip.  The 21272 could have two or four D-chips and the 21274 could have two, four, or eight D-chips.

The 21272 and 21274 were used extensively by Digital, Compaq and Hewlett Packard in their entry-level to mid-range AlphaServers and in all models of the AlphaStation. It was also used in third-party products from Alpha Processor, Inc. (later known as API NetWorks) such as their UP2000+ motherboard.

Irongate

AMD developed two Alpha 21264-compatible chipsets, the Irongate, also known as the AMD-751, and its successor, Irongate-2, also known as the AMD-761. These chipsets were developed for their Athlon microprocessors but due to AMD licensing the EV6 bus used in the Alpha from Digital, the Athlon and Alpha 21264 were compatible in terms of bus protocol. The Irongate was used by Samsung in their UP1000 and UP1100 motherboards. The Irongate-2 was used by Samsung in their UP1500 motherboard.

See also
 AlphaVM: A full DEC Alpha system emulator running on Windows or Linux. It contains a high-performance emulator of the Alpha CPU.
 Clustered Multi-threading
 Alpha 21364
 Alpha 21464

Notes

References
 Compaq Computer Corporation (July 1999). Alpha 21264 Microprocessor Hardware Reference Manual.
 Compaq Computer Corporation (June 2001). 21264/EV68CB and 21264/EV68DC Hardware Reference Manual.
 Compaq Computer Corporation (March 2002). 21264/EV67 Microprocessor Hardware Reference Manual.
 Compaq Computer Corporation (March 2002). 21264/EV68A Microprocessor Hardware Reference Manual.
 Gronowski, Paul E. et al. (1998). "High Performance Microprocessor Design". IEEE Journal of Solid-State Circuits, Volume 33, Number 5, pp. 676–686.
 Gwennap, Linley (28 October 1996). "Digital 21264 Sets New Standard". Microprocessor Report, Volume 10, Number 14. MicroDesign Resources.
 Kessler, R. E.; McLellan, E. J. and Webb, D. A. (1998) "The Alpha 21264 Microprocessor Architecture". Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors. pp. 90–95.
 Kessler, R. E. (1999). "The Alpha 21264 Microprocessor". IEEE Micro, March–April 1999. pp. 24–36.
 Leibholz, Daniel and Razdan, Rahul (1997). "The Alpha 21264: A 500 MHz Out-of-Order Execution Microprocessor". Proceedings of Compcon '97. pp. 28–36.
 Matson, M. et al. "Circuit Implementation of a 600MHz Superscalar RISC Microprocessor". Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors. pp. 104–110.

Further reading

 Benschneider, B.J. et al. (2000). "A 1 GHz Alpha microprocessor". ISSCC Digest of Technical Papers, pp. 86–87.
 Clouser, J. et al. (July 1999). "A 600-MHz superscalar floating-point processor". IEEE Journal of Solid-State Circuits 34 (7): pp. 1026–1029.
 Fischer, T.; Leibholz, D. (1998). "Design trade offs in stall-control circuits for 600 MHz instruction queues". ISSCC Digest of Technical Papers, pp. 232–234, 444.
 Gieseke, B.A. et al. (1997). "A 600 MHz superscalar RISC microprocessor with out-of-order execution". ISSCC Digest of Technical Papers, pp. 176–177, 451.
 Gronowski, Paul E. et al. (May 1998). "High-performance microprocessor design". IEEE Journal of Solid-State Circuits 33 (5): pp. 676–686.
 Hokinson, R. et al. (2001). "Design and migration challenges for an Alpha microprocessor in a 0.18 μm copper process". ISSCC Digest of Technical Papers, pp. 320–321, 460.

DEC microprocessors
Superscalar microprocessors
64-bit microprocessors


The Alpha 21364, code-named "Marvel", also known as EV7 is a microprocessor developed by Digital Equipment Corporation (DEC), later Compaq Computer Corporation, that implemented the Alpha instruction set architecture (ISA).

History

The Alpha 21364 was revealed in October 1998 by Compaq at the 11th Annual Microprocessor Forum, where it was described as an Alpha 21264 with a 1.5 MB 6-way set-associative on-die secondary cache, an integrated Direct Rambus DRAM memory controller and an integrated network controller for connecting to other microprocessors. Changes to the Alpha 21264 core included a larger victim buffer, which was quadrupled in capacity to 32 entries, 16 for the Dcache and 16 for the Scache. It was reported by the Microprocessor Report that Compaq considered implementing minor changes to branch predictor to improve branch prediction accuracy and doubling the miss buffer in capacity to 16 entries instead of 8 in the Alpha 21264.

It was expected to be taped-out in late 1999, with samples available in early 2000 and volume shipments in late 2000. However, the original schedule was delayed, with the tape-out in April 2001 instead of late 1999. The Alpha 21364 was introduced on 20 January 2002 when systems using the microprocessor debuted. It operated at 1.25 GHz, but production models in the AlphaServer ES47, ES80 and GS1280 operated at 1.0 GHz or 1.15 GHz. Unlike previous Alpha microprocessors, the Alpha 21364 was not sold on the open market.

The Alpha 21364 was originally intended to be succeeded by the Alpha 21464, code-named EV8, a new implementation of the Alpha ISA with four-way simultaneous multithreading (SMT). It was first presented in October 1999 at the 12th Annual Microprocessor Forum, but was cancelled on 25 June 2001 at a late stage of development.

Development

The development of the Alpha 21364 was most focused on features that would improve memory performance and multiprocessor scalability. The focus on memory performance was the result of a forward-looking article published in Microprocessor Report titled, "It's the Memory, Stupid!" written by Richard L. Sites, who co-led the definition of the Alpha architecture. The article concluded that, "Over the coming decade, memory subsystem design will be the only important design issue for microprocessors."

Description

The Alpha 21364 was an Alpha 21264 with a 1.75 MB on-die secondary cache, two integrated memory controllers and an integrated network controller.

Core

The Alpha 21364's core is based on the EV68CB, a derivative of the Alpha 21264. The only modification was a larger victim buffer, now quadrupled in capacity to 32 entries. The 32 entries of victim buffer is divided equally into 16 entries each for the Dcache and Scache. Although the Alpha 21364 is a fourth-generation implementation of the Alpha Architecture, aside from this modification, the core is otherwise identical to the EV68CB derivative of the Alpha 21264.

Scache

The secondary cache (termed "Scache") is a unified cache with a capacity of 1.75 MB. It is 7-way set associative, uses a 64-byte line size, and has a write-back policy. The cache is protected by single-bit error correction, double-bit error detection (SECDED) error-correcting code (ECC). It is connected to the cache controller by a 128-bit data path. Access to the cache is fully pipelined, yielding a sustainable bandwidth of 16 GB/s at 1.0 GHz.

The time required for data requested from the cache to when it can be used is 12 cycles. The 12-cycle latency was considered by observers, such as the Microprocessor Report, to be significant. The latency of the Scache was not reduced further as it would have not improved performance. The Alpha 21264 core upon which the Alpha 21364 was based on was designed to use an external cache built from commodity SRAM, which has a significantly higher latency than the on-die Scache of the Alpha 21364. Thus, it could only accept data at a limited rate. Once improving latency saw no further gains, the designers focused on reducing the power consumed by the Scache. Compaq was not willing to remedy this deficiency as it would have required the Alpha 21264 core to be modified significantly. The high latency of the Scache permitted the cache tags be looked up first to determine if the Scache contained the requested data and in which bank it was located in before powering up the Scache bank and accessing it. This avoided unproductive Scache accesses, reducing power consumption.

The tag store consisted of 5.75 million transistors and data store of 108 million transistors.

Memory controller

The Alpha 21364 has two integrated memory controllers that support Rambus DRAM (RDRAM) that operate at two thirds of the microprocessor's clock frequency, or 800 MHz at 1.2 GHz. Compaq designed custom memory controllers for the Alpha 21364, giving them capabilities not found in standard RDRAM memory controllers such as having all the 128 pages open, reducing the access latency to those pages; and proprietary fault-tolerant features.

Each memory controller provides five RDRAM channels that support PC800 Rambus inline memory modules (RIMMs). Four of the channels are used to provide memory, while the fifth is used to provide RAID-like redundancy. Each channel is 16 bits wide, operates at 400 MHz and transfers data on both the rising and falling edges of the clock signal (double data rate) for a transfer rate of 800 MT/s, yielding 1.6 GB/s of bandwidth. The total memory bandwidth of the eight channels is 12.8 GB/s.

Cache coherence is provided by the memory controllers. Each memory controller has a cache coherence engine. The Alpha 21364 uses a directory cache coherence scheme where part of the memory is used to store Modified, Exclusive, Shared, Invalid (MESI) coherency data.

R-box
The R-box contains the network router. The network router connected the microprocessor to other microprocessors using four ports named North, South, East and West. Each port consisted of two 39-bit unidirectional links operating at 800 MHz. 32 bits were for data and 7 bits were for ECC. The network router also has a fifth port, used for I/O. This port connects to an IO7 application-specific integrated circuit (ASIC), which was a bridge to an AGP 4x channel and two PCI-X buses. The I/O port consisted of two unidirectional 32-bit links operating at 200 MHz, yielding a peak bandwidth of 3.2 GB/s. The I/O port link operated at a quarter of the clock frequency to simplify the design of the I/O ASIC.

The Alpha 21364 can connect to as many as 127 other microprocessors using two network topologies: shuffle and an 2D torus. The shuffle topology had more direct paths to other microprocessors, reducing latency and therefore improving performance, but was limited to connecting up to eight microprocessors as a result of its nature. The 2D torus topology enabled the network to feature up to 128 microprocessors.

In multiprocessing systems, each microprocessor is a node with its own memory. Accessing the memory of other nodes is possible, but with a latency. The latency increases with distance, thus the Alpha 21364 implements non-uniform memory access (NUMA) multiprocessing. I/O is also distributed in an identical fashion. An Alpha 21364 microprocessor in a multiprocessing system did not have to have its RIMM slots populated with memory or its I/O port populated with devices. It could use another microprocessor's memory and I/O.

Fault tolerance

The Alpha 21364 could operate in lock-step for fault-tolerant computers. This feature was a result in Compaq's decision to migrate Tandem's Himalaya fault-tolerant servers from the MIPS architecture to Alpha. The machines however never used the microprocessor as the decision to phase out the Alpha in favor of the Itanium was made before the availability of the Alpha 21364.

Fabrication

The Alpha 21364 contained 152 million transistors. The die measured 21.1 mm by 18.8 mm for an area of 397 mm². It was fabricated by International Business Machines (IBM) in their 0.18 µm, seven-level copper complementary metal–oxide–semiconductor (CMOS) process. It was packaged in a 1,443-land flip-chip land grid array (LGA). It used a 1.65 V power supply and a 1.5 V external interface for a maximum power dissipation of 155 W at 1.25 GHz.

Alpha 21364A

The Alpha 21364A, code-named EV79, previously EV78, was a further development of the Alpha 21364. It was intended to be the last Alpha microprocessor developed. Scheduled to be introduced in 2004, it was cancelled on 23 October 2003, with HP cited performance and schedule issues as reasons. A replacement, the EV7z was announced on the same day.

A prototype of the microprocessor was presented by Hewlett-Packard at the International Solid-State Circuits Conference in February 2003. It operated at 1.45 GHz, had a die area of 251 mm², used a 1.2 V power supply, and dissipated 100 W (estimated).

The Alpha 21364A was to have improved upon the Alpha 21364 by featuring higher clock frequencies in the range of ~1.6 to ~1.7 GHz and support for 1066 Mbit/s RDRAM memory. It was to be fabricated by IBM in their 0.13 µm silicon on insulator (SOI) process. As a result of the more advanced process, there were reductions in die size, power supply voltage (1.2 V compared to 1.65 V), and in power consumption and dissipation.

EV7z

The EV7z was a further development of the Alpha 21364. It was the last Alpha microprocessor developed and introduced. The EV7z became known on 23 October 2003 when HP announced they had cancelled the Alpha 21364A and would be replacing it with the EV7z. The EV7z was introduced on 16 August 2004 when the only computer using the microprocessor, AlphaServer GS1280, was introduced. It was discontinued on 27 April 2007 when the computer it was featured in was discontinued. It operated at 1.3 GHz, supported PC1066 RIMMs and was fabricated in the same 0.18 µm process as the Alpha 21364. Compared to the Alpha 21364, the EV7z was 14 to 16 percent faster, but was still slower than the Alpha 21364A it replaced, which was estimated to outperform the Alpha 21364 by 25 percent at 1.5 GHz.

Notes

References
 "EV7 AlphaServers unleashed as chip line heads into sunset". (21 January 2003). The Register.
 Bannon, Peter (4 January 2002). "Alpha 21364 (EV7)".
 Compaq Computer Corporation. Compiler Writer’s Guide for the 21264/21364, Revision 2.0, January 2002.
 Diefendorff, Keith (6 December 1999). "Compaq Chooses SMT for Alpha". Microprocessor Report, Volume 13, Number 16.
 Glaskowsky, Peter N. (24 March 2003). "Moore, Moore and More at ISSCC". Microprocessor Report.
 Grodstein, Joel; et al. (2002). "Power and CAD considerations for the 1.75Mbyte, 1.2GHz L2 cache on the Alpha 21364 CPU". GLVLSI '02.
 Gwenapp, Linley (26 October 1998). "Alpha 21364 to Ease Memory Bottleneck". Microprocessor Report.
 Hewlett-Packard Development Company, L.P. (20 January 2004). HP Introduces Most Powerful Generation of AlphaServer Systems. Press release.
 Hewlett-Packard Development Company, L.P. (16 August 2004). HP Expands UNIX Server and StorageWorks Portfolios to Offer Customers Greater Value and Flexibility on Standards-based Platforms. Press release.
 Jain, A. et al. (2001). "A 1.2 GHz Alpha microprocessor with 44.8 GB/s chip pin bandwidth". ISSCC Digest of Technical Papers.
 Krewell, Kevin (24 March 2003). "EV7 Stresses Memory Bandwidth". Microprocessor Report.
 Mukherjee, Shubhendu S.; Bannon, Peter; Lang, Steve; Spink, Aaron; Webb, David (2002). "The Alpha 21364 Network Architecture". IEEE Micro. pp. 26–35.
 Seznec, Andre; et al. (25–29 May 2002). "Design Tradeoffs for the Alpha EV8 Conditional Branch Predictor". Proceedings of the 29th IEEE-ACM International Symposium on Computer Architecture.
 Shannon, Terry (24 October 2003). "HP is Dealt a Delay in its HP-UX OS and Alpha Processor Roadmap". Shannon Knows HPC, Volume 10, Number 51.

Further reading

 Kowaleski, J.A., Jr. et al. (2003). "Implementation of an Alpha microprocessor in SOI". ISSCC Digest of Technical Papers. pp. 248–249, 491.
 Tsuk, M. et al. (2001). "Modeling and measurement of the Alpha 21364 package". Electrical Performance of Electrical Packaging. pp. 283–286.
 Xanthopoulos, T. et al. (2001). "The design and analysis of the clock distribution network for a 1.2GHz Alpha microprocessor". ISSCC Digest of Technical Papers. pp. 402–403.

DEC microprocessors
Superscalar microprocessors
64-bit microprocessors


Floyd Edwin Yount (December 19, 1915 – October 26, 1973) was a professional baseball player. He played six games in two seasons in Major League Baseball, four for the Philadelphia Athletics in 1937 and two for the Pittsburgh Pirates in 1939, primarily as an outfielder. Yount enjoyed a minor league career which lasted until 1951, except for three seasons missed during World War II.

External links

Major League Baseball outfielders
Philadelphia Athletics players
Pittsburgh Pirates players
Williamsport Grays players
Oakland Oaks (baseball) players
Portsmouth Cubs players
Little Rock Travelers players
Oklahoma City Indians players
Syracuse Chiefs players
Toronto Maple Leafs (International League) players
Hamilton Red Wings (baseball) players
Buffalo Bisons (minor league) players
Newton-Conover Twins players
Baseball players from North Carolina
1915 births
1973 deaths
People from Newton, North Carolina
Mooresville Moors players


Dizengoff Center () is a shopping mall at the intersection of Dizengoff Street and King George Street in Tel Aviv, Israel. The mall is named for Meir Dizengoff, the first mayor of Tel Aviv.

History

Dizengoff Center, designed by Israeli architect Yitzhak Yashar, was Israel's first mall. The center was built on the site of the Nordiya neighborhood. Construction began in 1972, and the first store opened five years later in 1977. The rest of the mall was finished in 1983.

On March 4, 1996, during the Jewish holiday of Purim, the Dizengoff Center suicide bombing outside Dizengoff Center killed 13 people, many of them youngsters in costume.

On July 13, 2022, the first Lego store in Israel opened in Dizengoff Center.

Overview
The mall has around 420 stores, one movie theater (Lev Dizengoff, with 6 screens), restaurants, an internet cafe, a design center holding exhibitions from around the world (Soho), specialty stores (comic books, video games, gadgets, stamp-collecting, posters), a rooftop swimming pool and two gyms. The mall is divided into two parts and straddles both sides of Dizengoff Street with the two parts linked by skywalks and underground passages. The underground parts of Dizengoff Center include a bomb shelter fully equipped with toilets and showers using underground aquifer waters, and rooms for families.

The mall also hosts weekly events. Every Friday (except for Jewish holidays) the mall hosts the "Food Fair", Israel's largest food festival, with foods from a large variety of cuisines. On Thursdays and Fridays it hosts a designers boutique, which includes fashion and jewelry from 40 designers. Also on Thursdays and Fridays, it hosts an "alternative therapies fair."

The mall is visited by about 40,000 people on weekdays, around 45,000 people on Fridays, and about 80,000 during the holidays.

Towers
Two towers were built upon the mall – a residential tower above the northern part of the mall commonly referred to as the "Dizengoff Tower," and an office tower above the south-western part of the mall commonly referred to as "Top Tower". The mall also has a big underground parking lot.

Dizengoff Tower was commissioned by developer Abraham Pilz and Azorim, and designed by the architect Mordechai Ben Horin. The building was inspired by the shape of a rose. It has 21 floors and stands  tall. The architect wanted to maximize the perimeter of the building and allow each apartment to have a view in two directions, hence the zig-zag shape. The original design called for 320 small apartments of approximately , but many were combined, for an eventual total of 226. The floor area is . An expansion to the base of the tower was approved in the 2010s, but the plan was rejected following an appeal.

Gallery

See also
 Azrieli Center
 List of shopping malls in Israel

References

External links

 Dizengoff Center virtual tour

Buildings and structures in Tel Aviv
Shopping malls in Israel
Shopping malls established in 1983
1983 establishments in Israel
Tourist attractions in Tel Aviv


Brugman is a Dutch toponymic surname meaning "bridgeman". It could refer to someone living near a bridge, or as an occupational name to a bridge keeper. In some cases it refers to someone originally from Bruges (Brugge) in West Flanders. Notable people with the surname include:

 Alyssa Brugman (born 1974), Australian author
 Gastón Brugman (born 1992), Uruguayan football midfielder
 Jaycob Brugman (born 1992), American baseball player
 John Brugman (c.1400–1473), Franciscan preacher in the Low Countries
 Mathias Brugman (1811–1868), Puerto Rican revolutionary leader
 Til Brugman (1888–1958), Dutch poet and linguist

See also
 Brugmann
 Brugmans
 Bruggeman

References

Dutch-language surnames
Dutch toponymic surnames
Occupational surnames

de:Brugman
nl:Brugman


The Barylli Quartet was a celebrated Austrian string quartet classical musical ensemble. It was first brought together in Vienna during the War by Walter Barylli, Konzertmeister of the Vienna Philharmonic Orchestra from 1939, but was re-founded in 1945. The reformed quartet actually appeared in public performance only from 1951 to 1960. In that period it was the 'home' quartet of the Vienna Musikverein.

Personnel
1st violin - Walter Barylli
2nd violin - Otto Strasser
Viola - Rudolf Streng
Cello - Richard Krotschak, Emanuel Brabec
Many of the famous HI—FI Westminster Records recordings are with Emanuel Brabec.

Origins
Walter Barylli (born in Vienna in 1921-2022) studied at the Vienna Music Academy with the Philharmonic Konzertmeister Franz Mairecker, and in Munich with Florizel von Reuter. In 1936 Barylli gave his first public performance as a soloist in Munich, and made his first gramophone recordings in Berlin. Over the next two years he made an international career as a soloist: but realizing the difficulty of a career as a travelling soloist in the turmoil of the late 1930s he instead won a place at the Vienna Philharmonic Orchestra, of which he became Konzertmeister in 1939. The quartet was first formed from leading members of the Vienna Philharmonic, during the war. It was then reformed in 1945, but its work in public performance was mainly confined to the period 1951-1960.

Closely associated with the Vienna Musikverein, their work was principally with classic repertoire such as Beethoven, Mozart, Schubert, Schumann and Brahms. They gave many concerts in Europe and overseas. Among their various recordings are a complete Beethoven cycle for Westminster Records and a near-complete Mozart cycle. They performed at the Salzburg Festival, from which at least two live concerts (from 1956, Mozart Quintet with Antoine de Bavier, and 1958, of Beethoven, Schubert and Hindemith), have also survived as recordings. Their principal collaborations in chamber music were with Antoine de Bavier, Edith Farnadi, Jörg Demus, Paul Badura-Skoda and the violist Wilhelm Hübner.

Emanuel Brabec, the group's cellist in 1958, taught at the Vienna Academy and was teacher of Nikolaus Harnoncourt.

Notes and references

External links
 Barylli discography .
 Barylli Quartet discography with album covers etc., .

Austrian string quartets
Musicians from Vienna


was the common-law wife of the Chinese Communist scholar and poet Guo Moruo. She is often referred to in Chinese sources as Guo Anna (), the way Guo Moruo called her. Satō Tomiko spent about 20 years with Guo, in Japan and in China, until they were separated by the war, and they had five children together.

Biography
Tomiko Satō was the eldest of eight children in the family of a Japanese Protestant minister in the Ōhira village, Kurokawa District, Miyagi Prefecture (north-eastern Honshū). In her teens she studied at a Baptist boarding school in Sendai, the capital of the prefecture. At 21, rebelling against the prospect of an arranged marriage, she left her home prefecture and went to Tokyo, where she found a job with St Luke's Hospital as a student nurse.

Satō's relationship with Guo Moruo started in the summer of 1916, about a year after her arrival to Tokyo. A friend of Guo, named Chen Longji (陈龙骥), happened to be treated for tuberculosis at St Luke's Hospital. Guo, who had just completed his first year of study in Japan, visited his sick friend in the hospital on his trip to Tokyo, but the patient died soon. After the death of his friend, Guo met her when visiting the hospital to request the dead friend's X-ray records. Satō was sharing Guo's grief over the death of his friend, and once Guo returned to Okayama, they started regularly exchange letters. By December, Guo Moruo convinced Satō to leave Tokyo and join him in Okayama.

Satō and Guo had their first child, a son, in December 1917.

Satō and Guo's union was vehemently opposed by both of their families, and ill-received by the community they were in.

In April 1923, Satō moved with Guo and their three children to Shanghai. They had financial difficulties, and in February 1924 she went to Japan, taking the children along, but returned to Shanghai in mid-November. Guo was very active in the Communist underground movement. The Nationalist Government put out an arrest warrant for Guo in 1928.  He escaped to Japan again and lived with Sato for ten years.  But they were under constant Japanese surveillance.

War years
After the Marco Polo Bridge Incident in July 1937, the war between China and Japan started in earnest. On July 25, Guo managed to escape Japan and to return to China where his arrest warrant was rescinded. As his attempts to get Sato and their children out of Japan later that year were frustrated by the Japanese government, she was left alone to take care of the children in wartime Japan.  She had little money and lived a marginal life with the children. She resisted the pressure of the authorities to have them naturalized as Japanese citizens; this protected them from the prospect of being conscripted and possibly sent to fight against their father's country. The four elder children were able to enter Kyoto Imperial University; all graduated, and became specialists in industrial chemistry, aquaculture, architecture, and mathematics.  The youngest child was educated at Qinghua University in Beijing.

Postwar years
After WWII she tried to contact Guo.  He avoided all attempts to meet.  She discovered that he had taken another wife and had had several more children.  She wrote long letters to his close friends whom she knew from their earlier years.  In 1949 Zhou Enlai arranged for her to live in Dalian, China.  She became a Chinese citizen.  In 1983 she was appointed to the Sixth CPPCC National Committee and served consecutively thereafter. She finally saw Guo Moruo for the last time shortly before he died in 1978 in his hospital.

When interviewed in 1980 by , who was to write her biography, Satō summarized her life story as follows: "I am a stray dog all my life, but whatever bitterness can be said about this bitter life, that was because of my own foolishness". She died in 1995, aged 101.

Children
All her children achieved successful lives in China.

 Eldest son Guo HeFu 郭和夫 (1917-1994), Member of Academica Sinica in Chemistry. She lived with him in Dalian.
 Guo Bo 郭博 (1920-), architect, cinematographer and member of various professional and Shanghai institutions including the Soong Ching Ling Foundation 宋庆龄基金会理事.
 Guo FuSheng 郭复生 (亦叫佛生, 1923-), Chinese Academy of Science.
 Daughter Guo ShuZhen 郭淑瑀 (1925-). She married Lin AiSin 林爱信  and had a daughter Lin Cong 林丛 who studied in Japan.  She became a Japanese citizen and now teaches in Japan as Rina Fujita 藤田梨那.
 Youngest son Guo ZhiHong 郭志鸿 (1932-), Visiting professor at Central Conservatory of Music 中央音乐学院客座教授.

Bibliography

References

Works cited

Further reading
 谷輔林, 唐燕能. "郭沫若和他的日本妻子" (Guo Moruo and his Japanese wife). 上海: 學林出版社, 1999. . .

1894 births
1995 deaths
Japanese centenarians
Japanese Protestants
People from Miyagi Prefecture
Women centenarians
Chinese expatriates in Japan


The three primary objectives of nuclear reactor safety systems as defined by the U.S. Nuclear Regulatory Commission are to shut down the reactor, maintain it in a shutdown condition and prevent the release of radioactive material.

Reactor protection system (RPS)
A reactor protection system is designed to immediately terminate the nuclear reaction. By breaking the nuclear chain reaction, the source of heat is eliminated. Other systems can then be used to remove decay heat from the core. All nuclear plants have some form of reactor protection system.

Control rods
Control rods are a series of rods that can be quickly inserted into the reactor core to absorb neutrons and rapidly terminate the nuclear reaction. They are typically composed of actinides, lanthanides, transition metals, and boron, in various alloys with structural backing such as steel. In addition to being neutron absorbent, the alloys used also are required to have at least a low coefficient of thermal expansion so that they do not jam under high temperatures, and they have to be self-lubricating metal on metal, because at the temperatures experienced by nuclear reactor cores oil lubrication would foul too quickly.

Safety injection / standby liquid control
Boiling water reactors are able to SCRAM the reactor completely with the help of their control rods. In the case of a loss of coolant accident (LOCA), the water-loss of the primary cooling system can be compensated with normal water pumped into the cooling circuit. On the other hand, the standby liquid control (SLC) system (SLCS) consists of a solution containing boric acid, which acts as a neutron poison and rapidly floods the core in case of problems with the stopping of the chain reaction.

Pressurized water reactors also can SCRAM the reactor completely with the help of their control rods.  PWRs also use boric acid to make fine adjustments to reactor power level, or reactivity, using their Chemical and Volume Control System (CVCS). In the case of LOCA, PWRs have three sources of backup cooling water, high pressure injection (HPI), low pressure injection (LPI), and core flood tanks (CFTs).  They all use water with a high concentration of boron.

Essential service water system

The essential service water system (ESWS) circulates the water that cools the plant's heat exchangers and other components before dissipating the heat into the environment. Because this includes cooling the systems that remove decay heat from both the primary system and the spent fuel rod cooling ponds, the ESWS is a safety-critical system. Since the water is frequently drawn from an adjacent river, the sea, or other large body of water, the system can be fouled by seaweed, marine organisms, oil pollution, ice and debris. In locations without a large body of water in which to dissipate the heat, water is recirculated via a cooling tower.

The failure of half of the ESWS pumps was one of the factors that endangered safety in the 1999 Blayais Nuclear Power Plant flood, while a total loss occurred during the Fukushima I and Fukushima II nuclear accidents in 2011.

Emergency core cooling systems

Emergency core cooling systems (ECCS) are designed to safely shut down a nuclear reactor during accident conditions. The ECCS allows the plant to respond to a variety of accident conditions (e.g. LOCAs) and additionally introduce redundancy so that the plant can be shut down even with one or more subsystem failures. In most plants, ECCS is composed of the following systems:

High pressure coolant injection system
The High Pressure Coolant Injection (HPCI) System consists of a pump or pumps that have sufficient pressure to inject coolant into the reactor vessel while it is pressurized. It is designed to monitor the level of coolant in the reactor vessel and automatically inject coolant when the level drops below a threshold. This system is normally the first line of defense for a reactor since it can be used while the reactor vessel is still highly pressurized.

Automatic depressurization system

The Automatic Depressurization System (ADS) consists of a series of valves which open to vent steam several feet under the surface of a large pool of liquid water (known as the wetwell or torus) in pressure suppression type containments (typically used in boiling water reactor designs), or directly into the primary containment structure in other types of containments, such as large-dry or ice-condenser containments (typically used in pressurized water reactor designs). The actuation of these valves depressurizes the reactor vessel and allows lower pressure coolant injection systems to function, which have very large capacities in comparison to the high pressure systems. Some depressurization systems are automatic in function, while others may require operators to manually activate them. In pressurized water reactors with large dry or ice condenser containments, the valves of the system are called Pilot-operated relief valves.

Low pressure coolant injection system
An LPCI is an emergency system which consists of a pump that injects a coolant into the reactor vessel once it has been depressurized. In some nuclear power plants an LPCI is a mode of operation of a residual heat removal system, also known as an RHR or RHS but is generally is called LPCI. It is also not a stand-alone valve or system.

Core spray system (only in BWRs)
This system uses spargers (pipes fitted with an array of many small spray nozzles) within the reactor pressure vessel to spray water directly onto the fuel rods, suppressing the generation of steam. Reactor designs can include core spray in high-pressure and low-pressure modes.

Containment spray system
This system consists of a series of pumps and spargers that spray coolant into the upper portion of the primary containment structure. It is designed to condense the steam into liquid within the primary containment structure in order to prevent overpressure and overtemperature, which could lead to leakage, followed by involuntary depressurization.

Isolation cooling system
This system is often driven by a steam turbine to provide enough water to safely cool the reactor if the reactor building is isolated from the control and turbine buildings. Steam turbine driven cooling pumps with pneumatic controls can run at mechanically controlled adjustable speeds, without battery power, emergency generator, or off-site electrical power. The Isolation cooling system is a defensive system against a condition known as station blackout. This system is not part of the ECCS and does not have a low coolant accident function. For pressurized water reactors, this system acts in the secondary cooling circuit and is called Turbine driven auxiliary feedwater system.

Emergency electrical systems
Under normal conditions, nuclear power plants receive power from generator. However, during an accident a plant may lose access to this power supply and thus may be required to generate its own power to supply its emergency systems. These electrical systems usually consist of diesel generators and batteries.

Diesel generators
Diesel generators are employed to power the site during emergency situations. They are usually sized such that a single one can provide all the required power for a facility to shut down during an emergency.  Facilities have multiple generators for redundancy. Additionally, systems that are required to shut down the reactor have separate electrical sources (often separate generators) so that they do not affect shutdown capability.

Motor generator flywheels
Loss of electrical power can occur suddenly and can damage or undermine equipment. To prevent damage, motor-generators can be tied to flywheels that can provide uninterrupted electrical power to equipment for a brief period. Often they are used to provide electrical power until the plant electrical supply can be switched to the batteries and/or diesel generators.

Batteries
Batteries often form the final redundant backup electrical system and are also capable of providing sufficient electrical power to shut down a plant.

Containment systems
Containment systems are designed to prevent the release of radioactive material into the environment.

Fuel cladding
The fuel cladding is the first layer of protection around the nuclear fuel and is designed to protect the fuel from corrosion that would spread fuel material throughout the reactor coolant circuit. In most reactors it takes the form of a sealed metallic or ceramic layer. It also serves to trap fission products, especially those that are gaseous at the reactor's operating temperature, such as krypton, xenon and iodine. Cladding does not constitute shielding, and must be developed such that it absorbs as little radiation as possible. For this reason, materials such as magnesium and zirconium are used for their low neutron capture cross sections.

Reactor vessel
The reactor vessel is the first layer of shielding around the nuclear fuel and usually is designed to trap most of the radiation released during a nuclear reaction. The reactor vessel is also designed to withstand high pressures.

Primary containment
The primary containment system usually consists of a large metal and/or concrete structure (often cylindrical or bulb shaped) that contains the reactor vessel. In most reactors it also contains the radioactively contaminated systems. The primary containment system is designed to withstand strong internal pressures resulting from a leak or intentional depressurization of the reactor vessel.

Secondary containment
Some plants have a secondary containment system that encompasses the primary system. This is very common in BWRs because most of the steam systems, including the turbine, contain radioactive materials.

Core catching
In case of a full melt-down, the fuel would most likely end up on the concrete floor of the primary containment building.  Concrete can withstand a great deal of heat, so the thick flat concrete floor in the primary containment will often be sufficient protection against the so-called China Syndrome.   The Chernobyl plant didn't have a containment building, but the core was eventually stopped by the concrete foundation.  Due to concerns that the core would melt its way through the concrete, a "core catching device" was invented, and a mine was quickly dug under the plant with the intention to install such a device.  The device contains a quantity of metal designed to melt, diluting the corium and increasing its heat conductivity; the diluted metallic mass could then be cooled by water circulating in the floor.  Today, all new Russian-designed reactors are equipped with core-catchers in the bottom of the containment building.

The AREVA EPR, SNR-300, SWR1000, ESBWR, and Atmea I reactors have core catchers.

The ABWR has a thick layer of basaltic concrete floor specifically designed to catch the core.

Standby gas treatment
A standby gas treatment system (SGTS) is part of the secondary containment system. The SGTS system filters and pumps air from secondary containment to the environment and maintains a negative pressure within the secondary containment to limit the release of radioactive material.

Each SGTS train generally consists of a mist eliminator/roughing filter; an electric heater; a prefilter; two absolute (HEPA) filters; an activated charcoal filter; an exhaust fan; and associated valves, ductwork, dampers, instrumentation and controls. The signals that trip the SGTS system are plant-specific; however, automatic trips are generally associated with the electric heaters and a high temperature condition in the charcoal filters.

Ventilation and radiation protection
In case of a radioactive release, most plants have a system designed to remove radioactivity from the air to reduce the effects of the radioactivity release on the employees and public. This system usually consists of containment ventilation that removes radioactivity and steam from primary containment. Control room ventilation ensures that plant operators are protected. This system often consists of activated charcoal filters that remove radioactive isotopes from the air.

See also
 Boiling water reactor safety systems
 Nuclear accidents in the United States
 Nuclear safety in the U.S.
 Passive nuclear safety
 World Association of Nuclear Operators

References

Standards
 American National Standard, ANSI N18.2, “Nuclear Safety Criteria for the Design of Stationary Pressurized Water Reactor Plants,” August 1973.
 IEEE 279, “Criteria for Protection Systems for Nuclear Power Generating Stations.”

Nuclear reactor safety
Systems
Nuclear power plant components


Usun (; , Uhun) is a rural locality (a selo), the only inhabited locality, and the administrative center of Kyuletsky 1-y Rural Okrug () in Vilyuysky District of the Sakha Republic, Russia, located  from Vilyuysk, the administrative center of the district. Its population as of the 2010 Census was 801, up from 743 recorded during the 2002 Census.

Facilities
It has a high school, agricultural enterprise, kindergarten, shop, communication center, district hospital, bank.

References

Notes

Sources
Official website of the Sakha Republic. Registry of the Administrative-Territorial Divisions of the Sakha Republic. Vilyuysky District.

External links
Weather
Weather details
News
WikiMapia

Rural localities in Vilyuysky District


The third season of Veronica Mars, an American drama television series created by Rob Thomas, began airing on The CW in the United States on October 3, 2006. The season was produced by Warner Bros. Television, Silver Pictures Television, Stu Segall Productions, Inc and Rob Thomas Productions, and Joel Silver, Diane Ruggiero and Thomas served as executive producers. The third season comprises 20 episodes and concluded its initial airing on May 22, 2007.

The season continues the story of Veronica Mars (Kristen Bell), now a freshman studying at Hearst College while moonlighting as a private investigator under the wing of her detective father. The first mystery is established when her friend Parker Lee (Julie Gonzalo) becomes the latest victim of the Hearst serial rapist in a storyline begun in a second-season episode. Feeling guilty for not helping her, Veronica sets herself to catching the rapist. The next mystery, a murder, commences in the same episode that the identity of the rapist is discovered.

To increase viewership, the third season format was changed to include two separate mysteries that would be introduced and resolved in a series of non-overlapping story arcs. Three of the regulars in the second season were written out of the series, two new characters were introduced and two others were upgraded from recurring roles. The third season received generally mixed critical reviews compared to previous seasons.

Cast
The third season features a cast of ten actors who receive billing, an increase from the nine actors in the second. Kristen Bell portrays the titular Veronica Mars, a college student and skilled private detective. Jason Dohring plays Logan Echolls, Veronica's love interest. Ryan Hansen plays Logan's obnoxious friend Dick Casablancas. Percy Daggs III portrays Wallace Fennel, Veronica's best friend and frequent partner in solving mysteries. Francis Capra portrays Eli "Weevil" Navarro, the previous leader of the Pacific Coast Highway (PCH) biker gang and Veronica's friend. Enrico Colantoni plays Veronica's father Keith Mars, a private investigator and former Balboa County Sheriff.

Cindy "Mac" Mackenzie and Don Lamb, recurring characters in the first two seasons, were upgraded to series regulars in the third. Mac, portrayed by Tina Majorino, was a computer expert befriended by Veronica. Lamb, portrayed by Michael Muhney, was the Balboa County Sheriff who won the office from Keith in the recall election. The third season introduces two new series regulars, Julie Gonzalo portrays Parker Lee and Chris Lowell plays Stosh "Piz" Piznarski. Piz, named after the director of the pilot, Mark Piznarski, was created so that Veronica could have a male friend of middle-class status rather than of upper-class. He is Wallace's roommate and a friend of Veronica, and his campus radio show serves as a narrative device to capture the mood of the university. Parker is Mac's extroverted roommate at Hearst College and "everything that [she] is not", according to Thomas.

Regular characters who did not return for the third season were Duncan Kane (played by Teddy Dunn), who left the country with his daughter midway through the second season, Jackie Cook (Tessa Thompson), who returned to New York, and Cassidy Casablancas (Kyle Gallner), who died by suicide in the season two finale.

Episodes
Veronica is still living at home with her father Keith, and Piz and Parker are introduced as the respective roommates of Veronica's friends Wallace and Mac. Weevil takes a job at Hearst as a maintenance man, while Lamb continues to serve as Sheriff. During the season, Keith begins an affair with a married client, Wallace struggles to balance academics and sports, Mac begins dating again after previous failed relationships, and Dick has a breakdown and appeals to Logan for help. The season chronicles Veronica and Logan's failing attempts to maintain their relationship in the face of Veronica's mistrust.

Reception

Critical response
Reviews of the third season were mixed compared to the previous two seasons. Maureen Ryan of the Chicago Tribune praised Bell's performance, who she said deserved the "truckload of glowing press notices for her work as the tightly wound, emotionally resilient young detective". Ryan thought Veronica's relationship with Keith was "one of the best, if not the best, parent-child relationship on television", and described Logan and Veronica's on-screen chemistry as "sizzling". Stephanie Zacharek of Salon.com felt that although the third season "wasn't the strongest", it did show that Veronica Mars "could not only survive but continue to find ways to reinvigorate itself". Zacharek liked newcomer Piz, and realized how much she was going to miss the character Dick. Melanie McFarland of the Seattle Post-Intelligencer felt that Veronica Mars "easily has a few more seasons left in it", and described the writing as "unfailingly hysterical and clever". McFarland praised the cast as "without a doubt one of the most likable on television", and called Dohring "the most beloved of the bunch".

Keith McDuffee of TV Squad deemed the season "disappointing", mainly because the episodes offered nothing new: "most fans of Veronica Mars felt that season three was clearly its weakest". Eric Goldman of IGN said that the main issue was the shift in the overall tone, with a lighter feeling than the previous seasons. Goldman believed that Logan had been most affected by the tone change; he was robbed of his darker aspects and changed into an "increasingly extraneous character". The reviewer felt that despite the concerns over the final five episodes, the series ended with "three very strong episodes, with lots of strong dialogue". Goldman concluded that although third season "was very choppy", it still had "plenty of witty dialogue and a continually engaging performance by Kristen Bell as the title character". The Pittsburgh Post-Gazette opined that Veronica Mars had taken a dive "creatively", from "the mopier version of its theme song to stalled storylines". The reviewer felt that "the arcing mysteries had grown less convincing and compelling as time went on and were too drawn out". Fox News Channel's Bridget Byrne pointed out that Veronica had "gone from punky to—dare we say—preppy" in the third season.

The review aggregator website Rotten Tomatoes reported an approval rating of 89% with an average score of 8.13/10, based on 18 reviews. The website's critics consensus reads, "The third season of Veronica Mars continues to highlight the show's simple brilliance, offering more of the witty banter and quote-worthy dialogue the series is known for."

Ratings and awards
The third-season premiere was watched by 3.36 million American viewers, an increase from the 2.42 million viewers who viewed the second-season finale. Ratings remained stable for the first ten episodes, and the ninth episode featured the most viewers of the season with 3.44 million. Beginning with the eleventh episode, ratings dropped to a consistent viewership of a mid-2 million per episode, and the final episode before the hiatus was watched by 2.66 million viewers. When the series returned from its hiatus, viewers had decreased to 2.35 million, and the final two episodes garnered only 1.78 and 2.15 million viewers respectively.

The third season averaged 2.5 million viewers for all 20 episodes. Out of all regular primetime programming that aired during the 2006–2007 American television season, Veronica Mars ranked 138th out of 142, according to the Nielsen ratings system. The third season was nominated for two awards: Kristen Bell was nominated for the Saturn Award for Best Actress on Television, and the series was nominated for the Writers Guild of America Award for On-Air Promotion (Radio or Television).

Distribution

The first two seasons of Veronica Mars aired on UPN; however, in 2006, CBS Corporation and Warner Bros. decided to merge UPN and The WB into The CW. Paul Maguire, the spokesman for The CW, said that the series was picked up because "the critics are behind it and our research has consistently shown that Gilmore shared more audience commonality with Veronica than with any other show from UPN, except Top Model".

The third season was released in the US under the title Veronica Mars: The Complete Third Season as a widescreen six-disc Region 1 DVD box set on October 23, 2007, Region 2 on December 12, 2008, and Region 4 on February 11, 2009. In addition to all of the aired episodes, DVD extras included unaired scenes with introductions by Rob Thomas, a gag reel, and a webisode gallery with cast interviews and various set tours. Also included were the featurettes, "Going Undercover with Rob Thomas" commentary and "Pitching Season 4", an interview with Thomas discussing a new direction for the series that picks up years later, with Veronica as a rookie FBI agent.

The third season was simulcast in Canada by Fox 44. The series had previously been broadcast in Canada by the CTV Television Network and Sun TV. Despite airing the series to low ratings in the previous seasons, the United Kingdom's Living decided to air the series' third season. Network Ten began airing the third season in Australia on March 30, 2007. The series went on hiatus after the fourth episode on April 20, 2007, and resumed on the newly created Ten HD in 2008. The finale was aired on April 8, 2008. The third season was broadcast in New Zealand by TV2.

Cancellation and future
At the 2007 CW Upfront, Ostroff announced that Veronica Mars was not part of the new primetime lineup and was "not coming back". When asked if the series could continue with the FBI concept, Ostroff said that the series was completely gone "in any form". Upon the cancellation of the series, a group of fans calling themselves the "Cloud Watchers" sent more than 10,000 Mars bars to the CW, hoping that the network would reverse its decision and renew the series.

Thomas stated that he was interested in writing a feature film based on the series, in the interest of providing closure to the storylines and character arcs. In September 2008, Thomas told Entertainment Weekly that "I thought I had the idea broken, but I've hit a wall in the final act that I haven't quite figured out". Thomas explained that he was very busy writing for Cupid and Party Down, both of which he created. In January 2009, TV Guide reported that the film was Thomas' first priority after Cupid. Thomas noted that as well as writing the script, someone would need to pay for the film, but indicated that producer Joel Silver was ready to green-light the film. In late March, Thomas stated that although the film was not green-lit by the studio, the possibility was still there. Thomas revealed that the film would take place before Veronica's graduation, and feature Wallace, Logan, Mac and Weevil.

A film continuation, released in early 2014, was confirmed after a successful Kickstarter campaign launched by Rob Thomas which raised over $5.7 million.

In September 2018, an eight-episode fourth season was confirmed by Hulu, which was released on July 19, 2019.

References
General

Specific

External links

 Mars Investigations

Veronica Mars episodes
2006 American television seasons
2007 American television seasons


David Wayne may refer to:

David Wayne (1914–1995), American actor
David Wayne (musician) (1958–2005), American singer

See also

David Wain (born 1969), American comedian and director


The Hawaii Land Trust (HILT) is a non-profit organization established in Hawaii to “protect the lands that sustain us for current and future generations". The organization works with landowners to protect important areas by restricting commercial or other development. This protection is provided either by the landowner accepting a conservation easement on the land or by selling the land to HILT. As of 2018, the organization protected more than  across the state.

History
In January 2011, HILT was formed from the merger of the Kauai Public Land Trust, the Oahu Land Trust, the Maui Coastal Land Trust, and the Hawaii Island Land Trust.

The first executive director was Dale Bonar, followed by Ted Clement, Kawika Burgess, and then Laura Kaakua.

Originally named Hawaiian Islands Land Trust, in 2021 the organization renamed itself as Hawaii Land Trust, while retaining its acronym HILT.

Services
In addition to its core function of conserving important lands for future generations, HILT provides educational services, research and opportunities for recreation.

Talk Story on the Land
HILT offers a series of educational walks on its properties across the state.

Recreation
HILT properties are generally open to the public for activities such as fishing, camping and hiking.

Research
HILT staff conducts research on Hawaii's unique anchialine ponds and on the culture that surrounds them.

Properties
HILT has protected 57 properties on O'ahu, Kauai, Maui, Molokaʻi and Hawaiʻi Island, totaling more than .  are protected in HILT-owned preserves that are open to the public, and over  are protected via conservation easements that permanently restrict privately-owned land. Protected lands include coastlines, farms, ranches, cultural sites, traditional Hawaiian fishponds, native forests, and wetlands. HILT is actively working to protect additional coastlines, Hawaiian cultural landscapes, and lands that grow food for Hawaiʻi's people.

Waihee coastal dunes and wetlands refuge
The Waihee coastal dunes and wetlands refuge protects over  of land on Maui. The refuge includes  of coastal, spring-fed wetland,  of sand dune ecosystem, over  of shoreline and more than  of riparian habitat, totaling . It is located on the windward side of Maui, Hawaii.

The Maui Coastal Land Trust took ownership of this site in 2004 with support from Maui County. The property passed to HILT with the merger.

Active restoration programs have replaced invasive vegetation with native species, enhanced wildlife habitat and preserved archaeological and cultural resources. Restoration employs primarily volunteer labor, managed by professional staff.

The refuge is an important historical site, once hosting kingly residences, battles and Hawaiian legends. The refuge once hosted two fishing Hawaiian villages, an extensive inland Hawaiian fish ponds and several heiau (Hawaiian temple).

The refuge incorporates the last of Maui's large sand dunes that once stretched from Waihe'e to Makena, which once led to the island's nickname of "Sahara in the Pacific". The dunes are some  high.

Acquisition
The purchase was funded by Maui County (which provided $2,000,000), the United States Fish and Wildlife Service (FWS) (which contributed a further $2 million) and the National Oceanic and Atmospheric Administration (NOAA) (which provided $800,000). Management funding came from FWS, the National Resource Conservation Service Wetlands Reserve Program, NOAA, other grants and private funding from foundations, individuals and groups.

Climate change
Expected rising sea levels could inundate the sand dunes with seawater or transform them into sandy beaches. A  rise is expected to submerge 50-60% of the refuge. Adaptations that would preserve environmental and cultural values have yet to be developed/discovered. It is possible that the return to pre-development ecological status will provide sufficient resilience to provide protection.

Agriculture
Restoration plans include restoration of the fishpond and production of historically farmed crops such as taro. Nine taro patches are undergoing restoration, occupying about .

Some 200 sheep live in the refuge.

Conservation
Six endangered taxa, two endangered plants, and two endangered insects were found on the site. Eight endangered species have repopulated the refuge, including aeo (stilt), alae keokeo (coot), koloa (duck) and nene (goose).

When the property was first protected, 95% of the plants were invasive species. As of 2014, 70% of the flora in the wetland are native species.

Culture
Many of the important cultural and archaeological sites are located in sand dunes at or near the water. The dunes contains multiple burial sites. The dunes were fenced off to reduce foot traffic and exclude invasive predators. Thereafter endangered bird species began to nest on the dunes, acting as a natural vector and fertilizer for native plants.

Nu'u
HILT purchased the 82-acre Nu'u Preserve in 2011. The preserve provides habitat for endangered bird species and is home to numerous pre-contact archaeological sites, including petroglyphs and traditional house sites.

Nisei Veterans Peace Park
In 2015 the Nisei Veterans Memorial Center donated a  in Kahului to HILT, Maui and turned it into a memorial park to commemorate the service of the Nisei Veterans in World War II.

Maunawila Heiau
In 2015, HILT took ownership of Maunawila Heiau located on  in Hau'ula, Hawaii and began to restore it.

Kahili Beach Park
In 2013, the Trust acquired a 12.2-acre parcel at Kahili beach in Kilauea.

Wainiha
In 2008, HILT acquired a .4-acre parcel at Wainiha at Halelea.

Easements
HILT holds multiple conservation easements on 'Oahu, Maui, Hawaii Island and Kauai.

Recognition program
Each year HILT honors a major contributor to the environment as a Champion of the Land.

 United States Senator Brian Schatz (2017)
 Henk Rogers (2018)
 Founding members Susan and Jac Kean (2019)

HILT gave a separate honor to former Board Chair Peter Merriman in 2018.

References

External links

Maui News article on a Palaka Award being given to the founder of the trust
Official Facebook page

Land trusts in the United States
Environmental organizations based in Hawaii
Protected areas of Hawaii
2011 establishments in Hawaii
Organizations established in 2011


Fireproof is an album by the American singer-songwriter Dawn Landes. The album was released in January 2008 in Europe on Fargo Records, and March 4, 2008, in the United States on Cooking Vinyl Records.

The song "You Alone" was featured in the 2005 film Winter Passing.

Track listing

References

2008 albums
Cooking Vinyl albums


Jeff Kelly (born September 7, 1979) is a former American football quarterback in the National Football League. He was drafted in seventh round of the 2002 NFL Draft. He now is head coach of the Saraland High School Spartans, and has compiled a record of 118–35.

References

External links
Just Sport Stats

1979 births
Living people
People from Washington County, Alabama
Players of American football from Alabama
American football quarterbacks
Southern Miss Golden Eagles football players
Seattle Seahawks players
High school football coaches in Alabama


B'Sheva () is a weekly Hebrew language newspaper published in Israel.

The first issue of B'sheva, published by Arutz Sheva, appeared on July 19, 2002. It is distributed free on Thursdays in religious population centers.

Readership
The paper is read by 130,000 families and has been rated the largest circulation newspaper in Israel's religious sector. According to a 2005 TGI survey, B'Sheva was read by 6.1% of Israeli adults. In a TGI survey comparing the last half of 2009 with the same period in 2008, B'Sheva was fourth in market share for weekly newspapers.

See also
 Israeli newspapers

References

External links

2002 establishments in Israel
Free newspapers
Hebrew-language newspapers
Mass media in Petah Tikva
Weekly newspapers published in Israel
Newspapers established in 2002


Vijaya may refer to:

Places
 Vijaya (Champa), a city-state and former capital of the historic Champa in what is now Vietnam
 Vijayawada, a city in Andhra Pradesh, India

People
 Prince Vijaya of Sri Lanka (fl. 543–505 BC), earliest recorded king of Sri Lanka
 Vijaya (Satavahana) (c. 3rd century), Indian ruler of the Satavahana dynasty; successor of Yajna Sri Satakarni
 Vijaya Manikya I (r. 1488), king of Tripura
 Vijaya Manikya II (r. 1532–1563), king of Tripura
 Vijaya-Bhattarika (r. c. 650–655), regent of the Chalukya dynasty of southern India
 Vijaya Kumaratunga (1945–1988), Sri Lankan actor, social activist, politician
 Vijaya Nandasiri (1944–2016), Sri Lankan actor, director, producer, singer
 Vijaya Lakshmi Pandit, Indian diplomat and politician

In Hindu mythology
 Vijaya (bow), the personal bow of Shiva and Karna
 Vijaya, daughter of Dyutimat, the king of Madra Kingdom
 Jaya-Vijaya, the door-keepers of Vaikuntha, the realm of the god Vishnu in Hindu mythology

Other uses
 Vijaya Vauhini Studios, a film studio based in Chennai, India
 Vijaya (film), a 1973 Tamil film
 House of Vijaya, a Sinhalese royal dynasty
 Vijaya (font), a font introduced in Windows 7

See also
 Vijaya College (disambiguation)

 Vijay (disambiguation)
 Vijayalakshmi (disambiguation)
 Vijaynagar (disambiguation)
 Wijaya (disambiguation)
 Widjaja (disambiguation)


The Australian property market comprises the trade of land and its permanent fixtures located within Australia. The average Australian property price grew 0.5% per year from 1890 to 1990 after inflation, however rose from 1990 to 2017 at a faster rate and may be showing signs of a contracting economic bubble. House prices in Australia receive considerable attention from the media and the Reserve Bank and some commentators have argued that there is an Australian property bubble.

The residential housing market has seen drastic changes in prices in the past few decades. The property prices are soaring in major cities like Sydney, Melbourne, Adelaide, Perth, Brisbane and Hobart. The median house price in Sydney peaked at $780,000 in 2016.  However, with stricter credit policy and reduced interest from foreign investors in residential property, prices have started falling in all the major cities.  When compared with the soaring prices of 2017, the housing prices fell by 11.1% in Sydney and 7.2% in Melbourne in 2018.  In 2022 the residential rental market has seen a significant increase in rents, which has been described as a ‘rental crisis’.

Description

Composition

In 2011 there were 8.6m households with an average household size of 2.6 persons per household. Freestanding houses have historically comprised most building approvals, but recent data shows a trend towards higher density housing such as townhouses and units. Turnover rates vary across market cycles, but typically average 6% per year. Since 1999-2000 the proportion of households renting from state/territory housing authorities has declined from 6% to 3%  while the proportion renting privately increased from 20% to 26% in 2019-20.

Regional variations

The Australian property market is non-uniform, with high variation observed across the major cities and regional areas.

Sydney

In Sydney, as of March 2010, the Property Market's vacancy rate reached 0.53% signalling that the market is recovering, as these rates had reached 2% in August 2009. As of July 2015, the Property Market in Sydney has surged in the first Q of 2015, up 3.1%. Sydney's eastern and northern suburbs typically attract the highest prices, reflecting their desirability and premium location. The annual capital growth for houses and units in Sydney is 4.2% and 3.8% respectively.

Key issues

Affordability

In the late 2000s, housing prices in Australia, relative to average incomes, were among the highest in the world. As at 2011, house prices were on average six times average household income, compared to four times in 1990. This prompted speculation that the country was experiencing a real estate bubble, like many other countries.

Foreign investment has also been identified as a key driver of affordability issues, with recent years seeing particularly high capital inflows from Chinese investors.

Immigration to Australia
A number of economists, such as Macquarie Bank analyst Rory Robertson, assert that high immigration and the propensity of new arrivals to cluster in the capital cities is exacerbating the nation's housing affordability problem.  According to Robertson, Federal Government policies that fuel demand for housing, such as the currently high levels of immigration, as well as capital gains tax discounts and subsidies to boost fertility, have had a greater impact on housing affordability than land release on urban fringes.

The Productivity Commission Inquiry Report No. 28 First Home Ownership (2004) also stated, in relation to housing, "that Growth in immigration since the mid-1990s has been an important contributor to underlying demand, particularly in Sydney and Melbourne." This has been exacerbated by Australian lenders relaxing credit guidelines for temporary residents, allowing them to buy a home with a 10 percent deposit.

The RBA in its submission to the same PC Report also stated "rapid growth in overseas visitors such as students may have boosted demand for rental housing". However, in question in the report was the statistical coverage of resident population. The "ABS population growth figures omit certain household formation groups – namely, overseas students and business migrants who do not continuously stay for 12 months in Australia." This statistical omission lead to the admission: "The Commission recognises that the ABS resident population estimates have limitations when used for assessing housing demand. Given the significant influx of foreigners coming to work or study in Australia in recent years, it seems highly likely that short-stay visitor movements may have added to the demand for housing. However, the Commissions are unaware of any research that quantifies the effects."

Some individuals and interest groups have also argued that immigration causes overburdened infrastructure.

Foreign investment in residential property
In December 2008, the federal government introduced legislation relaxing rules for foreign buyers of Australian property. According to FIRB (Foreign Investment Review Board) data released in August 2009, foreign investment in Australian real estate had increased by more than 30% year to date. One agent said that "overseas investors buy them to land bank, not to rent them out. The houses just sit vacant because they are after capital growth."

Negative gearing

Australian property investors often apply the practice of negative gearing. This occurs when the investor borrows money to fund the purchase of the property, and the income generated by the property is less than the cost of owning and managing the property including interest. The investor is expecting that capital gains will compensate for the shortfall. Negative gearing receives considerable media and political attention due to the perceived distortion it creates on residential property prices. In anticipation of Labor being elected in the 2019 federal election, the banks issued less interest only loans which are used by many investors for negative gearing.

Residential rental market

In 2022 the Australian residential rental market saw an annual increase in rents of 12%, the strongest increase in 14 years. Across Australia the vacancy rate was 1%, when a rate below 2% is considered very competitive with affordability constraints impacting tenants. A number of sources have described the situation as a ‘rental crisis’.

The primary reason for the rental crisis is a lack of supply due to a variety of reasons, including existing landlords selling their rental properties which are being purchased by owner-occupiers and some landlords using their properties on the short term rental market such as Airbnb. Other commenators cited a lack of social housing being provided by the government. The COVID-19 pandemic also impacted the rental market with shared households reducing in size and city workers moving to regional areas due to increased remote work.

See also
Australian property bubble
Home ownership in Australia
Housing in Victoria

References

Real estate in Australia
Economy of Australia
Housing in Australia
Real estate bubbles of the 2000s


Upatissa is a Pali and Sinhala name. It may refer to:

 An alternate name for Sariputta, one of the chief male disciples of Gautama Buddha
Upatissagāma, his birthplace, near Rajgriha, in Magadha, India
 Upatissa (regent), chief minister and member of Prince Vijaya's followers, Sinhalese regent of the Kingdom of Tambapanni (505 BC–504 BC)
 Arahant Upatissa (Sri Lanka, 1st or 2nd century CE), the reputed author of the Vimuttimagga, an ancient Buddhist meditation manual
 Upatissa I of Anuradhapura, King of Anuradhapura (370–412)
 Upatissa II of Anuradhapura, King of Anuradhapura (525–526)
 Upatissa (Sri Lanka, 10th Century CE), reputed author of the Mahabodhivamsa
 Upatissa Gamanayake (1948–1989), former deputy leader of the Janatha Vimukthi Peramuna
Upatissagāma, capital of the Kingdom of Tambapanni in Sri Lanka

See also
Tissa (disambiguation)

Sinhalese masculine given names
Sinhalese given names