eval/f32-tanh.yaml

# Copyright 2023 Google LLC
#
# This source code is licensed under the BSD-style license found in the
# LICENSE file in the root directory of this source tree.

# ARM NEON
- name: xnn_math_f32_tanh__neonfma_expm1minus_rr1_lut8_p4h2ts_nr1recps1fma
- name: xnn_math_f32_tanh__neonfma_expm1minus_rr1_lut8_p4h2ts_nr2fma
- name: xnn_math_f32_tanh__neonfma_expm1minus_rr1_lut8_p4h2ts_nr2recps
- name: xnn_math_f32_tanh__neon_expm1minus_rr2_lut8_p4h2ts_nr2recps
- name: xnn_math_f32_tanh__aarch64_neonfma_expm1minus_rr1_lut8_p4h3ps_div
- name: xnn_math_f32_tanh__neonfma_expm1minus_rr1_lut8_p4h3ps_nr1recps1fma
- name: xnn_math_f32_tanh__neonfma_expm1minus_rr1_lut8_p4h3ps_nr1recps1fmaadj
- name: xnn_math_f32_tanh__neonfma_expm1minus_rr1_lut8_p4h3ps_nr2fma
- name: xnn_math_f32_tanh__neonfma_expm1minus_rr1_lut8_p4h3ps_nr2fmaadj
- name: xnn_math_f32_tanh__neonfma_expm1minus_rr1_lut8_p4h3ps_nr2recps
- name: xnn_math_f32_tanh__neonfma_expm1minus_rr1_lut8_p4h3ps_nr2recpsadj
- name: xnn_math_f32_tanh__neon_expm1minus_rr2_lut8_p4h3ps_nr2recps
- name: xnn_math_f32_tanh__aarch64_neonfma_expm1minus_rr1_p6h5ts_div
- name: xnn_math_f32_tanh__neonfma_expm1minus_rr1_p6h5ts_nr1recps1fma
- name: xnn_math_f32_tanh__neonfma_expm1minus_rr1_p6h5ts_nr1recps1fmaadj
- name: xnn_math_f32_tanh__neonfma_expm1minus_rr1_p6h5ts_nr2fma
- name: xnn_math_f32_tanh__neonfma_expm1minus_rr1_p6h5ts_nr2fmaadj
- name: xnn_math_f32_tanh__neonfma_expm1minus_rr1_p6h5ts_nr2recps
- name: xnn_math_f32_tanh__neonfma_expm1minus_rr1_p6h5ts_nr2recpsadj
- name: xnn_math_f32_tanh__neon_expm1minus_rr1_p6h5ts_nr2recps

# x86 SSE2
- name: xnn_math_f32_tanh__sse2_expm1minus_rr2_lut8_p4h2ts_nr1
- name: xnn_math_f32_tanh__sse2_expm1minus_rr2_lut8_p4h2ts_nr2
- name: xnn_math_f32_tanh__sse2_expm1minus_rr1_lut8_p4h3ps_div
- name: xnn_math_f32_tanh__sse2_expm1minus_rr2_lut8_p4h3ps_nr1
- name: xnn_math_f32_tanh__sse2_expm1minus_rr2_lut8_p4h3ps_nr2
- name: xnn_math_f32_tanh__sse2_expm1minus_rr2_lut8_p4h3ts_nr1
- name: xnn_math_f32_tanh__sse2_expm1minus_rr2_lut8_p4h3ts_nr2
- name: xnn_math_f32_tanh__sse2_expm1minus_rr1_p6h5ts_div
- name: xnn_math_f32_tanh__sse2_expm1minus_rr1_p6h5ts_nr1
- name: xnn_math_f32_tanh__sse2_expm1minus_rr1_p6h5ts_nr2

# x86 AVX
- name: xnn_math_f32_tanh__avx_expm1minus_rr1_lut4_p4h2ts_perm_div
- name: xnn_math_f32_tanh__avx_expm1minus_rr2_lut8_p4h2ts_nr1
- name: xnn_math_f32_tanh__avx_expm1minus_rr2_lut8_p4h2ts_nr2
- name: xnn_math_f32_tanh__avx_expm1minus_rr1_lut8_p4h3ps_div
- name: xnn_math_f32_tanh__avx_expm1minus_rr2_lut8_p4h3ps_nr1
- name: xnn_math_f32_tanh__avx_expm1minus_rr2_lut8_p4h3ps_nr2
- name: xnn_math_f32_tanh__avx_expm1minus_rr2_lut8_p4h3ts_nr1
- name: xnn_math_f32_tanh__avx_expm1minus_rr2_lut8_p4h3ts_nr2
- name: xnn_math_f32_tanh__avx_expm1minus_rr1_p6h5ts_div
- name: xnn_math_f32_tanh__avx_expm1minus_rr1_p6h5ts_nr1
- name: xnn_math_f32_tanh__avx_expm1minus_rr1_p6h5ts_nr2

# x86 FMA3
- name: xnn_math_f32_tanh__fma3_expm1minus_rr1_lut4_p4h3ts_perm_div
- name: xnn_math_f32_tanh__fma3_expm1minus_rr1_lut4_p4h3ts_perm_nr1adj
- name: xnn_math_f32_tanh__fma3_expm1minus_rr1_lut8_p4h3ps_div
- name: xnn_math_f32_tanh__fma3_expm1minus_rr1_lut8_p4h3ps_nr1
- name: xnn_math_f32_tanh__fma3_expm1minus_rr1_lut8_p4h3ps_nr1adj
- name: xnn_math_f32_tanh__fma3_expm1minus_rr1_p6h5ts_div
- name: xnn_math_f32_tanh__fma3_expm1minus_rr1_p6h5ts_nr1
- name: xnn_math_f32_tanh__fma3_expm1minus_rr1_p6h5ts_nr1adj

# x86 AVX2
- name: xnn_math_f32_tanh__avx2_expm1minus_rr1_lut4_p4h3ts_perm_div
- name: xnn_math_f32_tanh__avx2_expm1minus_rr1_lut4_p4h3ts_perm_nr1adj
- name: xnn_math_f32_tanh__avx2_expm1minus_rr1_lut8_p4h3ps_perm_div
- name: xnn_math_f32_tanh__avx2_expm1minus_rr1_lut8_p4h3ps_perm_nr1
- name: xnn_math_f32_tanh__avx2_expm1minus_rr1_lut8_p4h3ps_perm_nr1adj
- name: xnn_math_f32_tanh__avx2_expm1minus_rr1_lut8_p4h3ps_gather_div
- name: xnn_math_f32_tanh__avx2_expm1minus_rr1_lut8_p4h3ps_gather_nr1
- name: xnn_math_f32_tanh__avx2_expm1minus_rr1_lut8_p4h3ps_gather_nr1adj
- name: xnn_math_f32_tanh__avx2_expm1minus_rr1_p6h5ts_div
- name: xnn_math_f32_tanh__avx2_expm1minus_rr1_p6h5ts_nr1
- name: xnn_math_f32_tanh__avx2_expm1minus_rr1_p6h5ts_nr1adj

# x86 AVX512
- name: xnn_math_f32_tanh__avx512skx_expm1minus_rr1_lut4_p4h3ts_perm_div
- name: xnn_math_f32_tanh__avx512skx_expm1minus_rr1_lut4_p4h3ts_perm_nr1adj
- name: xnn_math_f32_tanh__avx512skx_expm1minus_rr1_lut8_p4h3ps_perm_div
- name: xnn_math_f32_tanh__avx512skx_expm1minus_rr1_lut8_p4h3ps_perm_nr1
- name: xnn_math_f32_tanh__avx512skx_expm1minus_rr1_lut8_p4h3ps_perm_nr1adj
- name: xnn_math_f32_tanh__avx512skx_expm1minus_rr1_lut8_p4h3ps_gather_div
- name: xnn_math_f32_tanh__avx512skx_expm1minus_rr1_lut8_p4h3ps_gather_nr1
- name: xnn_math_f32_tanh__avx512skx_expm1minus_rr1_lut8_p4h3ps_gather_nr1adj
- name: xnn_math_f32_tanh__avx512skx_expm1minus_rr1_p6h5ts_div
- name: xnn_math_f32_tanh__avx512skx_expm1minus_rr1_p6h5ts_nr1
- name: xnn_math_f32_tanh__avx512skx_expm1minus_rr1_p6h5ts_nr1adj

# Wasm SIMD
- name: xnn_math_f32_tanh__wasmsimd_expm1minus_rr1_lut8_p4h3ps_div_abs_min
- name: xnn_math_f32_tanh__wasmsimd_expm1minus_rr1_lut8_p4h3ps_div_abs_pmin
- name: xnn_math_f32_tanh__wasmsimd_expm1minus_rr1_lut8_p4h3ps_div_nabs_max
- name: xnn_math_f32_tanh__wasmsimd_expm1minus_rr1_lut8_p4h3ps_div_nabs_pmax
- name: xnn_math_f32_tanh__wasmsimd_expm1minus_rr1_p6h5ts_div_abs_min
- name: xnn_math_f32_tanh__wasmsimd_expm1minus_rr1_p6h5ts_div_abs_pmin
- name: xnn_math_f32_tanh__wasmsimd_expm1minus_rr1_p6h5ts_div_nabs_max
- name: xnn_math_f32_tanh__wasmsimd_expm1minus_rr1_p6h5ts_div_nabs_pmax

# Wasm
- name: xnn_math_f32_tanh__wasm_expm1minus_rr1_lut8_p4h3ps_div
- name: xnn_math_f32_tanh__wasm_expm1minus_rr1_p6h5ts_div

# Scalar
- name: xnn_math_f32_tanh__scalar_expm1minus_rr1_lut4_p4h2ts_div
- name: xnn_math_f32_tanh__scalar_expm1minus_rr1_lut4_p4h2ts_rcp
- name: xnn_math_f32_tanh__scalar_expm1minus_rr2_lut4_p4h2ts_div
- name: xnn_math_f32_tanh__scalar_expm1minus_rr1_lut4_p4h3ps_div
- name: xnn_math_f32_tanh__scalar_expm1minus_rr1_lut4_p4h3ts_div
- name: xnn_math_f32_tanh__scalar_expm1minus_rr2_lut4_p4h3ps_div
- name: xnn_math_f32_tanh__scalar_expm1minus_rr2_lut4_p4h3ts_div
- name: xnn_math_f32_tanh__scalar_expm1minus_rr1_lut8_p3h1ts_div
- name: xnn_math_f32_tanh__scalar_expm1minus_rr2_lut8_p3h1ts_div
- name: xnn_math_f32_tanh__scalar_expm1minus_rr1_lut8_p4h2ts_div
- name: xnn_math_f32_tanh__scalar_expm1minus_rr1_lut8_p4h2ts_rcp
- name: xnn_math_f32_tanh__scalar_expm1minus_rr2_lut8_p4h2ts_div
- name: xnn_math_f32_tanh__scalar_expm1minus_rr2_lut8_p4h2ts_rcp
- name: xnn_math_f32_tanh__scalar_expm1minus_rr1_lut8_p4h3ps_div
- name: xnn_math_f32_tanh__scalar_expm1minus_rr1_lut8_p4h3ts_div
- name: xnn_math_f32_tanh__scalar_expm1minus_rr1_lut8_p4h3ps_rcp
- name: xnn_math_f32_tanh__scalar_expm1minus_rr1_lut8_p4h3ts_rcp
- name: xnn_math_f32_tanh__scalar_expm1minus_rr2_lut8_p4h3ps_div
- name: xnn_math_f32_tanh__scalar_expm1minus_rr2_lut8_p4h3ts_div
- name: xnn_math_f32_tanh__scalar_expm1minus_rr2_lut8_p4h3ps_rcp
- name: xnn_math_f32_tanh__scalar_expm1minus_rr2_lut8_p4h3ts_rcp
- name: xnn_math_f32_tanh__scalar_expm1minus_rr1_lut16_p3h1ts_div
- name: xnn_math_f32_tanh__scalar_expm1minus_rr2_lut16_p3h1ts_div
- name: xnn_math_f32_tanh__scalar_expm1minus_rr1_lut16_p4h2ts_div
- name: xnn_math_f32_tanh__scalar_expm1minus_rr1_lut16_p4h2ts_rcp
- name: xnn_math_f32_tanh__scalar_expm1minus_rr2_lut16_p4h2ts_div
- name: xnn_math_f32_tanh__scalar_expm1minus_rr1_lut16_p4h3ps_div
- name: xnn_math_f32_tanh__scalar_expm1minus_rr1_lut16_p4h3ts_div
- name: xnn_math_f32_tanh__scalar_expm1minus_rr2_lut16_p4h3ps_div
- name: xnn_math_f32_tanh__scalar_expm1minus_rr2_lut16_p4h3ts_div
- name: xnn_math_f32_tanh__scalar_expm1minus_rr1_lut32_p3h1ts_div
- name: xnn_math_f32_tanh__scalar_expm1minus_rr2_lut32_p3h1ts_div
- name: xnn_math_f32_tanh__scalar_expm1minus_rr1_lut64_p3h1ts_div
- name: xnn_math_f32_tanh__scalar_expm1minus_rr2_lut64_p3h1ts_div
- name: xnn_math_f32_tanh__scalar_expm1minus_rr1_p6h4ts_div
- name: xnn_math_f32_tanh__scalar_expm1minus_rr2_p6h4ts_div
- name: xnn_math_f32_tanh__scalar_expm1minus_rr1_p6h5ps_div
- name: xnn_math_f32_tanh__scalar_expm1minus_rr1_p6h5ts_div
- name: xnn_math_f32_tanh__scalar_expm1minus_rr1_p6h5ps_rcp
- name: xnn_math_f32_tanh__scalar_expm1minus_rr1_p6h5ts_rcp
- name: xnn_math_f32_tanh__scalar_expm1minus_rr2_p6h5ps_div
- name: xnn_math_f32_tanh__scalar_expm1minus_rr2_p6h5ts_div
- name: xnn_math_f32_tanh__scalar_expm1plus_rr1_lut4_p4h2ts_div
- name: xnn_math_f32_tanh__scalar_expm1plus_rr2_lut4_p4h2ts_div
- name: xnn_math_f32_tanh__scalar_expm1plus_rr1_lut4_p4h3ps_div
- name: xnn_math_f32_tanh__scalar_expm1plus_rr1_lut4_p4h3ts_div
- name: xnn_math_f32_tanh__scalar_expm1plus_rr2_lut4_p4h3ps_div
- name: xnn_math_f32_tanh__scalar_expm1plus_rr2_lut4_p4h3ts_div
- name: xnn_math_f32_tanh__scalar_expm1plus_rr1_lut8_p3h1ts_div
- name: xnn_math_f32_tanh__scalar_expm1plus_rr2_lut8_p3h1ts_div
- name: xnn_math_f32_tanh__scalar_expm1plus_rr1_lut8_p4h2ts_div
- name: xnn_math_f32_tanh__scalar_expm1plus_rr2_lut8_p4h2ts_div
- name: xnn_math_f32_tanh__scalar_expm1plus_rr1_lut8_p4h3ps_div
- name: xnn_math_f32_tanh__scalar_expm1plus_rr1_lut8_p4h3ts_div
- name: xnn_math_f32_tanh__scalar_expm1plus_rr2_lut8_p4h3ps_div
- name: xnn_math_f32_tanh__scalar_expm1plus_rr2_lut8_p4h3ts_div
- name: xnn_math_f32_tanh__scalar_expm1plus_rr1_lut16_p3h1ts_div
- name: xnn_math_f32_tanh__scalar_expm1plus_rr2_lut16_p3h1ts_div
- name: xnn_math_f32_tanh__scalar_expm1plus_rr1_lut16_p4h2ts_div
- name: xnn_math_f32_tanh__scalar_expm1plus_rr2_lut16_p4h2ts_div
- name: xnn_math_f32_tanh__scalar_expm1plus_rr1_lut16_p4h3ps_div
- name: xnn_math_f32_tanh__scalar_expm1plus_rr1_lut16_p4h3ts_div
- name: xnn_math_f32_tanh__scalar_expm1plus_rr2_lut16_p4h3ps_div
- name: xnn_math_f32_tanh__scalar_expm1plus_rr2_lut16_p4h3ts_div
- name: xnn_math_f32_tanh__scalar_expm1plus_rr1_lut32_p3h1ts_div
- name: xnn_math_f32_tanh__scalar_expm1plus_rr2_lut32_p3h1ts_div
- name: xnn_math_f32_tanh__scalar_expm1plus_rr1_lut64_p3h1ts_div
- name: xnn_math_f32_tanh__scalar_expm1plus_rr2_lut64_p3h1ts_div
- name: xnn_math_f32_tanh__scalar_expm1plus_rr1_p6h4ts_div
- name: xnn_math_f32_tanh__scalar_expm1plus_rr2_p6h4ts_div
- name: xnn_math_f32_tanh__scalar_expm1plus_rr1_p6h5ps_div
- name: xnn_math_f32_tanh__scalar_expm1plus_rr1_p6h5ts_div
- name: xnn_math_f32_tanh__scalar_expm1plus_rr2_p6h5ps_div
- name: xnn_math_f32_tanh__scalar_expm1plus_rr2_p6h5ts_div

# Scalar+FMA
- name: xnn_math_f32_tanh__fma_expm1minus_rr1_lut4_p4h2ts_div
- name: xnn_math_f32_tanh__fma_expm1minus_rr1_lut4_p4h2ts_rcp
- name: xnn_math_f32_tanh__fma_expm1minus_rr2_lut4_p4h2ts_div
- name: xnn_math_f32_tanh__fma_expm1minus_rr1_lut4_p4h3ps_div
- name: xnn_math_f32_tanh__fma_expm1minus_rr1_lut4_p4h3ts_div
- name: xnn_math_f32_tanh__fma_expm1minus_rr1_lut4_p4h3ps_rcp
- name: xnn_math_f32_tanh__fma_expm1minus_rr1_lut4_p4h3ts_rcp
- name: xnn_math_f32_tanh__fma_expm1minus_rr2_lut4_p4h3ps_div
- name: xnn_math_f32_tanh__fma_expm1minus_rr2_lut4_p4h3ts_div
- name: xnn_math_f32_tanh__fma_expm1minus_rr1_lut8_p3h1ts_div
- name: xnn_math_f32_tanh__fma_expm1minus_rr2_lut8_p3h1ts_div
- name: xnn_math_f32_tanh__fma_expm1minus_rr1_lut8_p4h2ts_div
- name: xnn_math_f32_tanh__fma_expm1minus_rr1_lut8_p4h2ts_rcp
- name: xnn_math_f32_tanh__fma_expm1minus_rr2_lut8_p4h2ts_div
- name: xnn_math_f32_tanh__fma_expm1minus_rr2_lut8_p4h2ts_rcp
- name: xnn_math_f32_tanh__fma_expm1minus_rr1_lut8_p4h3ps_div
- name: xnn_math_f32_tanh__fma_expm1minus_rr1_lut8_p4h3ts_div
- name: xnn_math_f32_tanh__fma_expm1minus_rr1_lut8_p4h3ps_rcp
- name: xnn_math_f32_tanh__fma_expm1minus_rr1_lut8_p4h3ts_rcp
- name: xnn_math_f32_tanh__fma_expm1minus_rr2_lut8_p4h3ps_div
- name: xnn_math_f32_tanh__fma_expm1minus_rr2_lut8_p4h3ts_div
- name: xnn_math_f32_tanh__fma_expm1minus_rr1_lut16_p3h1ts_div
- name: xnn_math_f32_tanh__fma_expm1minus_rr2_lut16_p3h1ts_div
- name: xnn_math_f32_tanh__fma_expm1minus_rr1_lut16_p4h2ts_div
- name: xnn_math_f32_tanh__fma_expm1minus_rr1_lut16_p4h2ts_rcp
- name: xnn_math_f32_tanh__fma_expm1minus_rr2_lut16_p4h2ts_div
- name: xnn_math_f32_tanh__fma_expm1minus_rr1_lut16_p4h3ps_div
- name: xnn_math_f32_tanh__fma_expm1minus_rr1_lut16_p4h3ts_div
- name: xnn_math_f32_tanh__fma_expm1minus_rr2_lut16_p4h3ps_div
- name: xnn_math_f32_tanh__fma_expm1minus_rr2_lut16_p4h3ts_div
- name: xnn_math_f32_tanh__fma_expm1minus_rr1_lut32_p3h1ts_div
- name: xnn_math_f32_tanh__fma_expm1minus_rr2_lut32_p3h1ts_div
- name: xnn_math_f32_tanh__fma_expm1minus_rr1_lut64_p3h1ts_div
- name: xnn_math_f32_tanh__fma_expm1minus_rr2_lut64_p3h1ts_div
- name: xnn_math_f32_tanh__fma_expm1minus_rr1_p6h4ts_div
- name: xnn_math_f32_tanh__fma_expm1minus_rr2_p6h4ts_div
- name: xnn_math_f32_tanh__fma_expm1minus_rr1_p6h5ps_div
- name: xnn_math_f32_tanh__fma_expm1minus_rr1_p6h5ts_div
- name: xnn_math_f32_tanh__fma_expm1minus_rr1_p6h5ps_rcp
- name: xnn_math_f32_tanh__fma_expm1minus_rr1_p6h5ts_rcp
- name: xnn_math_f32_tanh__fma_expm1minus_rr2_p6h5ps_div
- name: xnn_math_f32_tanh__fma_expm1minus_rr2_p6h5ts_div
- name: xnn_math_f32_tanh__fma_expm1plus_rr1_lut4_p4h2ts_div
- name: xnn_math_f32_tanh__fma_expm1plus_rr2_lut4_p4h2ts_div
- name: xnn_math_f32_tanh__fma_expm1plus_rr1_lut4_p4h3ps_div
- name: xnn_math_f32_tanh__fma_expm1plus_rr1_lut4_p4h3ts_div
- name: xnn_math_f32_tanh__fma_expm1plus_rr2_lut4_p4h3ps_div
- name: xnn_math_f32_tanh__fma_expm1plus_rr2_lut4_p4h3ts_div
- name: xnn_math_f32_tanh__fma_expm1plus_rr1_lut8_p3h1ts_div
- name: xnn_math_f32_tanh__fma_expm1plus_rr2_lut8_p3h1ts_div
- name: xnn_math_f32_tanh__fma_expm1plus_rr1_lut8_p4h2ts_div
- name: xnn_math_f32_tanh__fma_expm1plus_rr2_lut8_p4h2ts_div
- name: xnn_math_f32_tanh__fma_expm1plus_rr1_lut8_p4h3ps_div
- name: xnn_math_f32_tanh__fma_expm1plus_rr1_lut8_p4h3ts_div
- name: xnn_math_f32_tanh__fma_expm1plus_rr2_lut8_p4h3ps_div
- name: xnn_math_f32_tanh__fma_expm1plus_rr2_lut8_p4h3ts_div
- name: xnn_math_f32_tanh__fma_expm1plus_rr1_lut16_p3h1ts_div
- name: xnn_math_f32_tanh__fma_expm1plus_rr2_lut16_p3h1ts_div
- name: xnn_math_f32_tanh__fma_expm1plus_rr1_lut16_p4h2ts_div
- name: xnn_math_f32_tanh__fma_expm1plus_rr2_lut16_p4h2ts_div
- name: xnn_math_f32_tanh__fma_expm1plus_rr1_lut16_p4h3ps_div
- name: xnn_math_f32_tanh__fma_expm1plus_rr1_lut16_p4h3ts_div
- name: xnn_math_f32_tanh__fma_expm1plus_rr2_lut16_p4h3ps_div
- name: xnn_math_f32_tanh__fma_expm1plus_rr2_lut16_p4h3ts_div
- name: xnn_math_f32_tanh__fma_expm1plus_rr1_lut32_p3h1ts_div
- name: xnn_math_f32_tanh__fma_expm1plus_rr2_lut32_p3h1ts_div
- name: xnn_math_f32_tanh__fma_expm1plus_rr1_lut64_p3h1ts_div
- name: xnn_math_f32_tanh__fma_expm1plus_rr2_lut64_p3h1ts_div
- name: xnn_math_f32_tanh__fma_expm1plus_rr1_p6h4ts_div
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- name: xnn_math_f32_tanh__fma_expm1plus_rr1_p6h5ps_div
- name: xnn_math_f32_tanh__fma_expm1plus_rr1_p6h5ts_div
- name: xnn_math_f32_tanh__fma_expm1plus_rr2_p6h5ps_div
- name: xnn_math_f32_tanh__fma_expm1plus_rr2_p6h5ts_div